F5F Stay Refreshed Hardware Desktop Significant contrast exists between the R5 1600AF and R5 3600 models.

Significant contrast exists between the R5 1600AF and R5 3600 models.

Significant contrast exists between the R5 1600AF and R5 3600 models.

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P
Peedy
Senior Member
641
04-29-2019, 06:01 PM
#11
Yes, that's correct.
P
Peedy
04-29-2019, 06:01 PM #11

Yes, that's correct.

S
Sasha01868
Member
81
04-29-2019, 06:58 PM
#12
Yes, I replied to it.
S
Sasha01868
04-29-2019, 06:58 PM #12

Yes, I replied to it.

A
Ac1dicBlitzz
Member
206
05-04-2019, 05:48 AM
#13
Only this interpretation applies.
A
Ac1dicBlitzz
05-04-2019, 05:48 AM #13

Only this interpretation applies.

I
i0cean
Member
218
05-13-2019, 11:41 AM
#14
I mean I'm clarifying your question. Could you provide more details?
I
i0cean
05-13-2019, 11:41 AM #14

I mean I'm clarifying your question. Could you provide more details?

C
Carlord3107
Junior Member
19
05-13-2019, 05:20 PM
#15
I'd appreciate seeing examples from others. I'll keep this thread open for a couple of days.
C
Carlord3107
05-13-2019, 05:20 PM #15

I'd appreciate seeing examples from others. I'll keep this thread open for a couple of days.

S
Stefandefijter
Junior Member
41
05-20-2019, 06:21 PM
#16
Good luck with that!
S
Stefandefijter
05-20-2019, 06:21 PM #16

Good luck with that!

M
mchawd
Junior Member
8
05-21-2019, 05:55 PM
#17
The goal isn't just speed, it's about overall efficiency. Power follows the formula Cl × V² × f, which should improve with a drop from 1.3 to 1. A smaller node size means less Cl needed for the same task. The calculation involving Cl(zen1 + idle) multiplied by other factors seems inconsistent with the expected ratio. It looks like you didn't address the original question, and this isn't really about binning.
M
mchawd
05-21-2019, 05:55 PM #17

The goal isn't just speed, it's about overall efficiency. Power follows the formula Cl × V² × f, which should improve with a drop from 1.3 to 1. A smaller node size means less Cl needed for the same task. The calculation involving Cl(zen1 + idle) multiplied by other factors seems inconsistent with the expected ratio. It looks like you didn't address the original question, and this isn't really about binning.

P
Poop_Head27
Posting Freak
820
05-22-2019, 04:03 PM
#18
Ops’ inquiry:
P
Poop_Head27
05-22-2019, 04:03 PM #18

Ops’ inquiry:

L
ladymorepork
Posting Freak
791
05-22-2019, 04:38 PM
#19
Exactly what you said, you didn't get their question addressed. The issue was purely about power, not performance. They're correct to raise concerns. The calculation (Cl(zen1+(at idle)) * 5.746 = 1/2 of Cl(zen2(at idle)) * 4) seems inconsistent. It suggests a significant difference in capacitive load between the two chips, even though one is newer. The more plausible explanation is that the measurements weren't identical—perhaps a different program was run on the newer chip.
L
ladymorepork
05-22-2019, 04:38 PM #19

Exactly what you said, you didn't get their question addressed. The issue was purely about power, not performance. They're correct to raise concerns. The calculation (Cl(zen1+(at idle)) * 5.746 = 1/2 of Cl(zen2(at idle)) * 4) seems inconsistent. It suggests a significant difference in capacitive load between the two chips, even though one is newer. The more plausible explanation is that the measurements weren't identical—perhaps a different program was run on the newer chip.

E
EliasEM05
Junior Member
16
05-30-2019, 04:41 AM
#20
Edited on October 26, 2024 by DandaCze due to misunderstanding
E
EliasEM05
05-30-2019, 04:41 AM #20

Edited on October 26, 2024 by DandaCze due to misunderstanding

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