Significant contrast exists between the R5 1600AF and R5 3600 models.
Significant contrast exists between the R5 1600AF and R5 3600 models.
It's accurate that there are five similar programs on those two platforms. The only part I can mention is that around 20% of users were using them, and thank you for being the first one to notice I wasn't focusing on performance.
It can add up in different ways. Higher generation doesn't always mean equal or lower power usage for the same performance. You usually need to move several generations before seeing a big jump in efficiency compared to older models. Another point about the 1600AF is that it's built on a 2000 series platform, not a 1000 series. The 1600AF is part of the Zen line, while the 1600 is from the Zen+ line. You're only skipping one generation, not two.
I was mainly discussing performance to clarify the comparison. Let's simplify: think of two cars—one is a budget family car, the other a supercar like a Lamborghini. When you idle in the family car, it uses less fuel than if you did the same in a supercar. That difference is noticeable, but not huge.
The gap between them is smaller, so a better comparison would be two supercars where one is slightly faster but uses only a tiny bit more fuel.
The calculation follows a straightforward formula: silicon power equals capacitive load multiplied by V squared times frequency. Performance isn't mentioned anywhere in this equation. I also emphasized Zen+ in every post I made. When shrinking nodes, each transistor experiences less capacitive load and needs less voltage to switch at a specific frequency—something observed by the OP when switching at 4GHz versus 1.3V for 3.4GHz. Adding more transistors can boost chip performance, similar to how a Carry Generate Adder uses more gates for faster switching with shorter delays. This speeds up clocking, though it doesn’t raise IPC directly; it just allows higher frequency operation. However, these IP blocks are voltage-controlled and turn off when idle. This is why AVX 512 demands lower clock speeds. The instructions are broad, requiring a huge number of transistors to activate and switch, causing spikes in capacitive load each time. Still, it remains more efficient than skipping AVX 512 if the processor can support it. Ultimately, even inactive blocks may leak depending on how the gate is powered.
The power consumption doesn't rise proportionally with more transistors, especially if voltage stays constant unless you hit a point where the CPU would fail. For example, 1600AF on the 2000 series and 3600 on the 3000 series represent only a small step, not a huge leap, showing that shrinking transistors isn't the sole factor.
At a specific point in the circuit, without power gating, the Zen 3+ core with comparable transistor count to a Zen 3 core consumes less power due to additional voltage domains. (I also notice it operates at a higher node, but both factors apply. There’s some internal analysis on the power compiler logs.) Skip the generations for a moment; certain blocks or pipeline stages include more transistors to boost IPC or reduce logic delays. What matters most is the node shrink. I’m not claiming generation alone determines everything, but the rise in transistor count shouldn’t double the capacitive load. For example, at 12nm, a 1600AF chip has 4.8GT; a 4600 at TSMC 7nm has 3.8GT, and at 12nm it’s 2.1GT. Even at 5.9GT at 12nm, that’s only about 1.23 times the transistor count. The calculations aren’t perfect—they’re simplified—and they don’t consider varying capacitances at different densities, so the numbers might not be entirely accurate.