Employing a complete system-on-chip as the power distribution network
Employing a complete system-on-chip as the power distribution network
Picture this scenario: the Z670 PCH chip matches the silicon of a ULV mobile i5, but with a distinct UEFI setup that transforms it into a PCH rather than a complete PC. This design mirrors how Chinese Loongson platforms are structured for premium systems. High-performance Loongson 3 chips function as CPUs, while laptop-focused Loongson 2s serve as SoCs. On powerful Loongson motherboards, you might find one or two Loongson 3 chips as the primary CPU and a Loongson 2 SoC handling the PCH role. The "specialized PCH" Loongson 7 chips are essentially Loongson 2s with compromised CPU cores. This approach also applies to the PS4, which uses a Marvell ARM SoC as the PCH for its APU.
You aim to achieve enhanced performance while consuming less energy, leveraging the versatility of a general-purpose CPU for tasks better suited to its broad capabilities.
For that, you need a chipset fan—many users dislike it. Also, the ULV i5 isn’t an SOC, and it’s not a Ryzen model.
Remove every PCH feature and convert it into a temporary IPMI setup. Definitely not feasible for many reasons.
Based on the assumption that the low-power chip includes a SoC, creating a unified PCH for high-power chips and the entire low-end SoC reduces the variety of dies needed. This insight stems from a real system design example: the Loongson 3 platform. Loongson didn’t develop dedicated full PCH chips themselves; instead, they utilized the Loongson 2 SoC as the PCH for their high-power Loongson 3 variants. Even the more recent Loongson 7 "dedicated PCH" models are essentially modified Loongson 2 dies with significantly underperforming or nearly nonfunctional CPU cores.
This wouldn’t make sense at all. In reality, more heat from the chipset and the CPU wouldn’t happen because they’re not SOCs. That would actually point to AMD chips instead.
Intel's ULV chips meet SiP requirements. The concept involves them creating an ULP SoC first, then building a top-tier CPU from just that SoC. Rather than making a separate PCH for the high-performance CPU, they reuse the identical ULP SoC as the power management controller for the CPU.