Discussion around X299 EVGA cards with PCI-E lanes.
Discussion around X299 EVGA cards with PCI-E lanes.
I have a query about M.2 and SLI on the X299 Dark. You mentioned planning to use SLI with dual speeds of 16x and 16x, assigning slots 1 and 4. You’re also considering using two NVMe SSDs in slots 2 and 3, and wondering if adding a card with USB 3.0 ports will affect performance or cause issues. Regarding the slot 6, you’re concerned it might indicate a problem with one M.2 device. Your question also asks about running cards at 8x each to preserve bandwidth. Please let me know if you need clarification on any of these points.
The instructions in EVGA manuals can be tricky to grasp, which is why I had to clarify. I understand that PCIe 1 uses the same bandwidth as PCIe 2, while PCIe 4 shares with PCIe 3. The top four devices are currently unused due to GPU demands. Using M.2 NVMe 2x won’t work with PCIe 6, but 4x remains free for any additions. Do I get it correctly? Essentially, you can still expand the PCIe setup if you follow these guidelines.
It should be fine. Storage devices generally run through the PCH. That's usually what happens. The PCIe 4x slots and M.2 slots share bandwidth. Seems to be an amount of flexibility with that bottom slot though. There's a table on the big PCB that the board ships with: (There's two "Hi-end 3SLI" options. The top one should be 2SLI) PE6 pulls from the PCH whenever both PE1 and PE4 are in 16x mode. PE6 might be able to pull from the CPU whenever either slot (PE1 and PE4) is reduced to 8x. I think, not sure.
Well, since I cannot guess through my crystal ball about future products, I will just say about the current 44 lane CPU. Slot 1: GPU 1 = (16 lanes from CPU) Slot 4: GPU 2 = (16 lanes from CPU), cumulative 32 lanes used M.2 (110 mm): PCIe NVMe 4x = (4 lanes from CPU) *Disables U.2 slot, 36 lanes cumulative M.2 (80 mm): PCIe NVMe 4x = (4 lanes from CPU), 40 lanes cumulative Under these conditions, if you put a non-video card into slot 6, this receives 4 lanes from the PCH (Chipset). How the additional 4 lanes for the 10th gen get distributed is anyones guess