Upgrade your Corsair Vengeance 4x8 3600 CL18 with a boosted overclock.
Upgrade your Corsair Vengeance 4x8 3600 CL18 with a boosted overclock.
Hey there! I'm looking to boost my (title) RAM using a Z390 pro with T-top and an i9 9900k. Want to know typical settings or targets for better performance? I'm aiming to squeeze in some extra speed without spending too much time tweaking. Hope this helps you skip the trial-and-error! Thanks!
The default setting is set at 18, 19, 19, 39. Raising the last number to 59 seems unusual. Also, the list of six numbers isn't explained—could you clarify what each one represents? @ddennis002
You noticed the timing details don’t match an ASUS or Gigabyte motherboard. The correct order and description should appear in your BIOS settings as shown: CAS Latency 16, tRCD 18, tRP 18, tRAS 36, tRC 54, tRW 18.
-The time between when the memory controller signals the memory module to read a column and when the data is actually read from the output pins is called latency (tCL). The delay from activating a row command to issuing a read or write instruction is referred to as RAS# to CAS# delay (tRCD). It sets the interval between these commands. The precharge period (tRP) manages the timing between precharge and activation commands for the same memory rank. Activating to precharge delay (tRAS) defines how long to wait after a bank active command before issuing a precharge command. Typically, tRAS equals tCL plus tRCD plus two cycles. Row cycle time (tRC) indicates the minimum clock cycles needed for a row to complete a full cycle, from activation to precharging. To achieve optimal performance, select the smallest value possible based on the formula tRC = tRAS + tRP. For instance, if your module has a tRAS of 36 cycles and tRP of 18 cycles, then the tRC should be 54 cycles. The write recovery time (tWR) is another key parameter, representing internal timing delays—usually between 3 to 10 clock cycles—after a valid write finishes before precharging can occur. A baseline of 1.5v is suggested for initial testing, then adjustments are made until stability is achieved. For CL18 kits, stable operation often reaches around 3800MHz with stock XMP timings; increasing CL and sub-timings may be necessary later. Depending on your application, higher frequency can improve performance, though tighter timings generally yield better results, particularly in Intel-based systems. Consider using a memory benchmark tool for comparison between stock and OC Aida memory benchmarks, or a pass mark will suffice.
Thanks for your assistance. I'll try the suggested times and let you know the results. If benchmarks show stability, I'll reduce voltages by 0.05 each step and test the lowest possible voltages. Regarding clock stability at 1.45, it seems safe to aim for tighter timing up to around 1.5. @ddennis002
Yes you could probably push them even tighter there is a point where the memroy IC won't beable to handle it. you might not even make it back to 1.5v it all depends on silicon lottery among other factors