The Ryzen 3600 Pin has detached!
The Ryzen 3600 Pin has detached!
Spoiler Socket AM4 / PGA1331 Name Designator DP2_AUXP A10 DP2_AUXN A11 VSS A12 TEST11 A13 TDI A14 VSS A15 TEST41 A16 SVT A17 VSS A18 THERMTRIP_L A19 MB_DATA[4] A20 VSS A21 MB_DQS_L[0] A22 MB_DATA[6] A23 VSS A24 MB_DATA[12] A25 MB_DATA[8] A26 VSS A27 MB_DATA[14] A28 MB_DATA[10] A29 VSS A3 VSS A30 MB_DATA[16] A31 MB_DM[2] A32 VSS A33 MB_DATA[23] A34 MB_DATA[28] A35 VSS A36 MB_DQS_L[3] A37 DP0_TXN[2] A4 RSVD A5 VSS A6 DP2_TXP[1] A7 DP2_TXN[1] A8 VSS A9 VSS AA1 VDDCR_CPU AA10 VSS AA11 VDDCR_CPU AA12 VSS AA13 USB_SS_1RXP AA2 VSS AA27 VDDIO_MEM_S3 AA28 VSS AA29 USB_SS_1RXN AA3 TEST31 AA30 VSS AA31 MA_ADD[0] AA32 MA_BANK[1] AA33 VDDIO_MEM_S3 AA34 MA_BANK[0] AA35 MA_ADD[10] AA36 VDDIO_MEM_S3 AA37 MB_EVENT_L AA38 MB_CLK_L[3] AA39 VSS AA4 P_HUB_TXP[1] AA5 VSS AA6 VDDCR_CPU AA7 P_HUB_RXN[1] AA8 VSS AA9 USB_SS_1TXP AB1 VSS AB10 VDDCR_CPU AB11 VSS AB12 VDDCR_CPU AB13 RSVD AB2 VDDIO_MEM_S3 AB27 VSS AB28 VDDIO_MEM_S3 AB29 VDDCR_CPU AB3 VSS AB30 VDDIO_MEM_S3 AB31 VDDIO_MEM_S3 AB32 VDDIO_MEM_S3 AB33 MA_RAS_L_ADD[16] AB34 MA_WE_L_ADD[14] AB35 VDDIO_MEM_S3 AB36 RSVD AB37 MB_PAROUT AB38 VDDIO_MEM_S3 AB39 TEST10 AB4 P_HUB_TXN[1] AB5 VDDCR_CPU AB6 VSS AB7 P_HUB_RXP[1] AB8 VDDCR_CPU AB9 USB_SS_1TXN AC1 VDDCR_CPU AC10 VSS AC11 VDDCR_CPU AC12 VSS AC13 VDDCR_CPU AC2 VSS AC27 VDDIO_MEM_S3 AC28 VSS AC29 USB_SS_2TXP AC3 VDDIO_MEM_S3 AC30 VSS AC31 VDDIO_MEM_S3 AC32 MA0_CS_L[0] AC33 MA1_CS_L[0] AC34 VDDIO_MEM_S3 AC35 MB_ADD[0] AC36 MB_BANK[1] AC37 VDDIO_MEM_S3 AC38 MB_ADD[10] AC39 USB_SS_2TXN AC4 VSS AC5 P_HUB_TXP[2] AC6 P_HUB_TXN[2] AC7 VSS AC8 VSS AC9 VSS AD1 VSS AD10 VDDCR_CPU AD11 VSS AD12 VDDCR_CPU AD13 USB_SS_2RXP AD2 VDDIO_MEM_S3 AD27 VSS AD28 VDDIO_MEM_S3 AD29 RSVD AD3 VSS AD30 VDDIO_MEM_S3 AD31 MA_CAS_L_ADD[15] AD32 MA1_ODT[0] AD33 VDDIO_MEM_S3 AD34 MA0_ODT[0] AD35 MB_RAS_L_ADD[16] AD36 VDDIO_MEM_S3 AD37 MB_BANK[0] AD38 MB_WE_L_ADD[14] AD39 VSS AD4 P_HUB_TXP[3] AD5 P_HUB_TXN[3] AD6 VDDCR_CPU AD7 P_HUB_RXN[0] AD8 VDDCR_CPU AD9 USB_SS_3RXP AE1 VDDCR_CPU AE10 VSS AE11 VDDCR_CPU AE12 VSS AE13 USB_SS_2RXN AE2 VSS AE27 VDDIO_MEM_S3 AE28 VSS AE29 VDDCR_CPU AE3 VDDIO_MEM_S3 AE30 VSS AE31 MA_ADD[13] AE32 VDDIO_MEM_S3 AE33 MA1_CS_L[1] AE34 MA0_CS_L[1] AE35 VDDIO_MEM_S3 AE36 MB0_CS_L[0] AE37 MB1_CS_L[0] AE38 VDDIO_MEM_S3 AE39 P_HUB_TXP[0] AE4 P_HUB_TXN[0] AE5 VDDCR_CPU AE6 VSS AE7 P_HUB_RXP[0] AE8 VSS AE9 USB_SS_3RXN AF1 VSS AF10 VDDCR_CPU AF11 VSS AF12 VDDCR_CPU AF13 VDDCR_CPU AF2 VDDIO_MEM_S3 AF27 VSS AF28 VDDIO_MEM_S3 AF29 USB_SS_0TXP AF3 VSS AF30 MA0_ODT[1] AF31 VDDIO_MEM_S3 AF32 MA_ADD_17 AF33 MA1_ODT[1] AF34 VDDIO_MEM_S3 AF35 MB_CAS_L_ADD[15] AF36 MB1_ODT[0] AF37 VDDIO_MEM_S3 AF38 MB0_ODT[0] AF39 USB_SS_0TXN AF4 VSS AF5 GFX_CLKP AF6 GFX_CLKN AF7 VSS AF8 VDDCR_CPU AF9 VSS AG1 VDDCR_CPU AG10 VSS AG11 VDDCR_CPU AG12 VSS AG13 VDDCR_CPU AG14 VSS AG15 VDDCR_CPU AG16 VSS AG17 VDDCR_CPU AG18 VSS AG19 USB_SS_3TXP AG2 VDDCR_CPU AG20 VSS AG21 VDDCR_CPU AG22 VSS AG23 VDDCR_CPU AG24 VSS AG25 VDDCR_CPU AG26 VSS AG27 VSS AG28 VSS AG29 USB_SS_3TXN AG3 VSS AG30 VSS AG31 VSS AG32 VDDIO_MEM_S3 AG33 VDDIO_MEM_S3 AG34 VDDIO_MEM_S3 AG35 MB1_CS_L[1] AG36 VDDIO_MEM_S3 AG37 MB_ADD[13] AG38 MB0_CS_L[1] AG39 VSS AG4 GPP_CLK0P AG5 GPP_CLK0N AG6 VDDCR_CPU AG7 VSS AG8 VSS AG9 X48M_X2 AH1 VSS AH10 VDDCR_CPU AH11 VSS AH12 VDDCR_CPU AH13 VSS AH14 VDDCR_CPU AH15 VSS AH16 VDDCR_CPU AH17 VSS AH18 VDDCR_CPU AH19 RSVD AH2 VSS AH20 VDDCR_CPU AH21 VSS AH22 VDDCR_CPU AH23 VSS AH24 VDDCR_CPU AH25 VSS AH26 VDDCR_CPU AH27 VSS AH28 VSS AH29 VDDCR_CPU AH3 VSS AH30 MA_DATA[36] AH31 MA_DATA[37] AH32 VSS AH33 MA_DATA[32] AH34 RSVD AH35 MB0_ODT[1] AH36 MB_ADD_17 AH37 MB1_ODT[1] AH38 VDDIO_MEM_S3 AH39 GPP_CLK1P AH4 GPP_CLK1N AH5 VDDCR_CPU AH6 GPP_CLK2P AH7 GPP_CLK2N AH8 VDDCR_CPU AH9 X48M_X1 AJ1 VDDCR_CPU AJ10 VSS AJ11 VDDCR_CPU AJ12 VSS AJ13 VDDCR_CPU AJ14 VDD_18_S5 AJ15 VDDP_S5 AJ16 VDDP_S5 AJ17 VDDCR_SOC_S5 AJ18 VDD_33_S5 AJ19 VDDCR_CPU AJ2 VDD_18 AJ20 VDD_33 AJ21 VDDCR_CPU AJ22 VSS AJ23 VDDCR_CPU AJ24 VSS AJ25 VSS AJ26 VSS AJ27 VSS AJ28 VSS AJ29 USB0_ZVSS AJ3 MA_DATA[33] AJ30 MA_DM[4] AJ31 VSS AJ32 MA_DQS_H[4] AJ33 MA_DQS_L[4] AJ34 VSS AJ35 VSS AJ36 VSS AJ38 MB_ZVSS AJ39 USB_SS_ZVSS AJ4 VSS AJ5 GPP_CLK3P AJ6 GPP_CLK3N AJ7 VSS AJ8 VSS AJ9 VSS AK1 VSS AK10 VDDCR_CPU AK11 VSS AK12 VDDCR_CPU AK13 VSS AK14 VDD_18_S5 AK15 VDDCR_SOC_S5 AK18 VDD_33_S5 AK19 SDA1/I2C3_SDA/AGPIO20 AK2 VDD_18 AK20 VDD_33 AK21 VSS AK22 VSS AK25 MA_DATA[57] AK26 MA_DATA[56] AK27 VSS AK28 MA_DATA[49] AK29 SCL1/I2C3_SCL/AGPIO19 AK3 MA_DATA[34] AK30 VSS AK31 MA_DATA[39] AK32 MA_DATA[38] AK33 RSVD AK34 VSS AK35 MB_DATA[37] AK36 VSS AK37 MB_DATA[36] AK38 MB_DATA[32] AK39 VSS AK4 USB3_ZVSS AK5 USB2_ZVSS AK6 VDDCR_CPU AK7 USB_SS_ZVDDP AK8 VDDCR_CPU AK9 USB_OC0_L/AGPIO16 AL1 VDDCR_CPU AL10 VSS AL11 VDDCR_CPU AL12 P_GPP_TXP[2]/SATA_TX0P AL13 VDDCR_CPU AL14 VDDBT_RTC_G AL15 RSVD AL16 RSVD AL17 RSVD AL18 RSVD AL19 LPC_PME_L/AGPIO22 AL2 RSVD AL20 RSVD AL21 VDDP_SENSE AL22 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 AL23 VSS AL24 MA_DATA[62] AL25 MA_DM[7] AL26 VSS AL27 MA_DATA[51] AL28 MA_DM[6] AL29 VDDCR_CPU AL3 VSS AL30 MA_DATA[45] AL31 MA_DATA[44] AL32 VSS AL33 MA_DATA[35] AL34 VSS AL35 VSS AL36 MB_DATA[33] AL37 MB_DM[4] AL38 VSS AL39 TEST46[13] AL4 WAKE_L/AGPIO2 AL5 VDDCR_CPU AL6 PCIE_RST_L/EGPIO26 AL7 AM4R1 AL8 VSS AL9 USB_OC1_L/TDI/AGPIO17 AM1 P_GPP_RXN[1] AM10 VSS AM11 RSVD AM12 P_GPP_TXN[2]/SATA_TX0N AM13 VSS AM14 VDDIO_AUDIO AM15 RSVD AM16 RSVD AM17 VDDP AM18 VDDP AM19 VDDCR_CPU AM2 VDDP AM20 RSVD AM21 SATA_ACT_L/AGPIO130 AM22 VSS_SENSE_B AM23 CORETYPE[0] AM24 MA_DATA[63] AM25 VSS AM26 MA_DATA[61] AM27 MA_DATA[50] AM28 VSS AM29 PWR_GOOD AM3 MA_DATA[52] AM30 MA_DM[5] AM31 VSS AM32 MA_DATA[41] AM33 MA_DATA[40] AM34 VSS AM35 MB_DQS_L[4] AM36 MB_DQS_H[4] AM37 VSS AM38 MB_DATA[38] AM39 SYS_RESET_L/AGPIO1 AM4 VSS AM5 TEST0 AM6 TEST1/TMS AM7 VDDCR_CPU AM8 P_GPP_RXP[1] AM9 VSS AN1 VDDCR_CPU AN10 P_GPP_RXN[3]/SATA_RX1N AN11 RSVD AN12 VDDCR_CPU AN13 P_GPP_TXP[3]/SATA_TX1P AN14 RSVD AN15 RSVD AN16 RSVD AN17 VDDP AN18 VDDP AN19 AGPIO9/SGPIO0_DATAOUT AN2 VDDP AN20 RSVD AN21 VSS AN22 FANIN0/AGPIO84 AN23 ESPI_RESET_L/KBRST_L AN24 VSS AN25 MA_DQS_L[7] AN26 MA_DATA[60] AN27 VSS AN28 MA_DQS_L[6] AN29 AGPIO23/SGPIO0_LOAD AN3 MA_DATA[53] AN30 VSS AN31 MA_DQS_H[5] AN32 MA_DQS_L[5] AN33 VSS AN34 VSS AN35 MB_DATA[34] AN36 VSS AN37 MB_DATA[39] AN38 MB_DATA[35] AN39 VSS AN4 PWR_BTN_L/AGPIO0 AN5 USB1_ZVSS AN6 VDDCR_CPU AN7 AGPIO6 AN8 CORETYPE[1] AN9 USB_OC3_L/TDO/AGPIO24 AP1 P_GPP_RXN[2]/SATA_RX0N AP10 P_GPP_RXP[3]/SATA_RX1P AP11 VDDCR_CPU AP12 P_GPP_TXP[1] AP13 P_GPP_TXN[3]/SATA_TX1N AP14 RSVD AP15 RSVD AP16 RSVD AP17 VDDP AP18 VDDP AP19 SLP_S5_L AP2 VDDP AP20 RSVD AP21 AGPIO5/DEVSLP0 AP22 FANOUT0/AGPIO85 AP23 VSS AP24 MA_DATA[58] AP25 MA_DQS_H[7] AP26 VSS AP27 MA_DATA[54] AP28 MA_DQS_H[6] AP29 VDDCR_CPU AP3 VSS AP30 MA_DATA[42] AP31 MA_DATA[47] AP32 VSS AP33 MA_DATA[46] AP34 VSS AP35 VSS AP36 MB_DATA[44] AP37 MB_DATA[45] AP38 VSS AP39 S5_MUX_CTRL/EGPIO42 AP4 RSMRST_L AP5 VSS AP6 AGPIO8 AP7 RTCCLK AP8 VDDCR_CPU AP9 USB_OC2_L/TCK/AGPIO18 AR1 P_GPP_RXP[2]/SATA_RX0P AR10 VSS AR11 P_GPP_TXN[0] AR12 P_GPP_TXN[1] AR13 VSS AR14 RSVD AR15 RSVD AR16 VSS AR17 RSVD AR18 RSVD AR19 VDDCR_CPU AR2 RSVD AR20 RSVD AR21 CLK_REQG_L/OSCIN/EGPIO132 AR22 VSS AR23 RSVD AR24 MA_DATA[59] AR25 VSS AR26 VSS AR27 MA_DATA[55] AR28 VSS AR29 S0A3_GPIO/AGPIO10/SGPIO0_CLK AR3 VSS AR30 MA_DATA[48] AR31 VSS AR32 MA_DATA[43] AR33 VSS AR34 VSS AR35 MB_DATA[40] AR36 MB_DATA[41] AR37 VSS AR38 MB_DM[5] AR39 AGPIO40/SGPIO0_DATAIN AR4 VSS AR5 AGPIO4 AR6 48M_OSC AR7 VSS AR8 P_GPP_RXP[0] AR9 VSS AT1 VSS AT10 USB_ZVSS AT11 P_GPP_TXP[0] AT12 VSS AT13 EGPIO100 AT14 ESPI_ALERT_L/LDRQ0_L/EGPIO108 AT15 VSS AT16 SPI_CS1_L/EGPIO118 AT17 EGPIO70 AT18 RSVD AT19 SLP_S3_L AT2 LAD3/EGPIO107 AT20 LAD2/EGPIO106 AT21 VSS AT22 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AT23 CLK_REQ2_L/AGPIO116 AT24 RSVD AT25 VSS AT26 VSS AT27 VSS AT28 VSS AT29 TEST2 AT3 RSVD AT30 VSS AT31 VSS AT32 VSS AT33 VSS AT34 MB_DM[6] AT35 MB_DATA[46] AT36 VSS AT37 MB_DQS_H[5] AT38 MB_DQS_L[5] AT39 VDDCR_CPU AT4 BLINK/AGPIO11 AT5 AGPIO3 AT6 VSS AT7 P0B_ZVSS AT8 P_GPP_RXN[0] AT9 AZ_RST_L AU1 USB_HSD2P AU10 USB_HSD2N AU11 VDDCR_CPU AU12 EGPIO98 AU13 SPI_DI/ESPI_DAT1/EGPIO120 AU14 VDDCR_CPU AU15 SPI_DO/ESPI_DAT0/EGPIO121 AU16 SPI_TPM_CS_L/AGPIO76 AU17 VSS AU18 LPCCLK1/EGPIO75 AU19 AZ_SYNC AU2 LPCCLK0/EGPIO74 AU20 VSS AU21 LPC_RST_L AU22 GENINT2_L/AGPIO90 AU23 VSS AU24 SCL0/I2C2_SCL/EGPIO113 AU25 VSS AU26 VSS AU27 MB_DQS_H[7] AU28 MB_DQS_L[7] AU29 VDDCR_CPU AU3 VSS AU30 MB_DATA[61] AU31 MB_DATA[51] AU32 VSS AU33 MB_DQS_H[6] AU34 MB_DATA[49] AU35 VSS AU36 MB_DATA[42] AU37 MB_DATA[47] AU38 VSS AU39 AZ_SDOUT AU4 AZ_SDIN1 AU5 VDDCR_CPU AU6 USB_HSD0P AU7 USB_HSD0N AU8 VDDCR_CPU AU9 USB_HSD3N AV10 VDDCR_CPU AV11 EGPIO96 AV12 EGPIO99 AV13 VDDCR_CPU AV14 SPI_HOLD_L/ESPI_DAT3/EGPIO133 AV15 SPI_WP_L/ESPI_DAT2/EGPIO122 AV16 VSS AV17 LPC_PD_L/AGPIO21 AV18 LPC_CLKRUN_L/AGPIO88 AV19 VSS AV2 VSS AV20 LAD1/EGPIO105 AV21 GENINT1_L/AGPIO89 AV22 VSS AV23 CLK_REQ1_L/AGPIO115 AV24 SDA0/I2C2_SDA/EGPIO114 AV25 VSS AV26 MB_DATA[63] AV27 MB_DATA[62] AV28 VSS AV29 AZ_SDIN0 AV3 MB_DATA[57] AV30 MB_DATA[60] AV31 VSS AV32 MB_DATA[55] AV33 MB_DQS_L[6] AV34 VSS AV35 MB_DATA[52] AV36 MB_DATA[43] AV37 VSS AV38 AZ_SDIN2 AV4 VDDCR_CPU AV5 SATA_ZVSS AV6 SATA_ZVDDP AV7 VDDCR_CPU AV8 USB_HSD3P AV9 VSS AW10 EGPIO95 AW11 EGPIO97 AW12 VSS AW13 SPI_CLK/ESPI_CLK/EGPIO117 AW14 SPI_CS2_L/ESPI_CS_L/EGPIO119 AW15 VSS AW16 AGPIO86 AW17 LFRAME_L/EGPIO109 AW18 VSS AW19 LAD0/EGPIO104 AW20 SERIRQ/AGPIO87 AW21 VSS AW22 SPKR/AGPIO91 AW23 RSVD AW24 VSS AW25 MB_DATA[59] AW26 MB_DATA[58] AW27 VSS AW28 MB_DM[7] AW29 AZ_BITCLK AW3 MB_DATA[56] AW30 VSS AW31 MB_DATA[50] AW32 MB_DATA[54] AW33 VSS AW34 MB_DATA[48] AW35 MB_DATA[53] AW36 VSS AW37 VSS AW4 X32K_X1 AW5 X32K_X2 AW6 VSS AW7 USB_HSD1P AW8 USB_HSD1N AW9 DP2_TXN[3] B10 VDDCR_SOC B11 TEST15 B12 TRST_L B13 VDDCR_SOC B14 TMS B15 RESET_L B16 VDDCR_SOC B17 SIC B18 VSS B19 VDDCR_SOC B20 MB_DATA[1] B21 MB_DQS_H[0] B22 VSS B23 MB_DATA[2] B24 MB_DATA[13] B25 VSS B26 MB_DQS_L[1] B27 MB_DATA[15] B28 VSS B29 DP0_TXN[1] B3 MB_DATA[20] B30 MB_DATA[17] B31 VSS B32 MB_DATA[22] B33 MB_DATA[18] B34 VSS B35 MB_DATA[24] B36 MB_DQS_H[3] B37 MB_DATA[30] B38 DP0_TXP[2] B4 VDDCR_SOC B5 DP2_TXP[0] B6 DP2_TXN[0] B7 VDDCR_SOC B8 DP2_TXP[3] B9 VSS C1 VDDCR_SOC C10 TEST16 C11 TEST14 C12 VDDCR_SOC C13 TDO C14 TCK C15 VDDCR_SOC C16 SVD C17 SID C18 VDDCR_SOC C19 DP0_TXN[0] C2 MB_DATA[5] C20 MB_DM[0] C21 VSS C22 MB_DATA[7] C23 MB_DATA[3] C24 VSS C25 MB_DATA[9] C26 MB_DQS_H[1] C27 VSS C28 MB_DATA[11] C29 DP0_TXP[1] C3 MB_DATA[21] C30 VSS C31 MB_DQS_L[2] C32 MB_DQS_H[2] C33 VSS C34 MB_DATA[19] C35 MB_DATA[29] C36 VSS C37 MB_DATA[31] C38 MB_DATA[26] C39 VDDCR_SOC C4 DP0_TXP[3] C5 DP0_TXN[3] C6 VDDCR_SOC C7 DP2_TXP[2] C8 DP2_TXN[2] C9 P_GFX_TXP[0] D1 DP1_HPD D10 TEST17 D11 VSS D12 TEST6 D13 DBREQ_L D14 VSS D15 ALERT_L D16 SVC D17 VSS D18 VSS D19 DP0_TXP[0] D2 MB_DATA[0] D20 VSS D21 VSS D22 VSS D23 VSS D24 VSS D25 MB_DM[1] D26 VSS D27 RSVD D28 VSS D29 VDDCR_SOC D3 VSS D30 VSS D31 VSS D32 VSS D33 VSS D34 VSS D35 VSS D36 MB_DM[3] D37 MB_DATA[27] D38 VSS D39 DP1_TXP[0] D4 DP1_TXN[0] D5 VSS D6 DP1_TXP[1] D7 DP1_TXN[1] D8 VSS D9 P_GFX_TXN[0] E1 DP2_HPD E10 VSS E11 DP_AUX_ZVSS E12 DBRDY E13 VSS E14 VDDCR_SOC_SENSE E15 PWROK E16 VSS E17 MA_DATA[0] E18 RSVD E19 VDDCR_SOC E2 VSS E20 VSS E21 RSVD E22 VSS E23 MA_DATA[10] E24 RSVD E25 VSS E26 VSS E27 MA_DATA[22] E28 VSS E29 P_GFX_TXP[1] E3 MA_DQS_L[3] E30 MA_DATA[30] E31 VSS E32 MA_CHECK[4] E33 MA_CHECK[5] E34 VSS E35 MB_DATA[25] E36 MB_CHECK[4] E37 VSS E38 MB_CHECK[5] E39 VSS E4 VSS E5 TEST28_H E6 TEST28_L E7 VSS E8 DP1_TXP[3] E9 VSS F1 VDDCR_SOC F10 DP1_AUXP F11 DP_ZVSS F12 VDDCR_SOC F13 VDDCR_CPU_SENSE F14 VSS_SENSE_A F15 VDDCR_SOC F16 VSS F17 MA_DATA[5] F18 VSS F19 P_GFX_TXP[2] F2 MA_DATA[7] F20 MA_DATA[12] F21 VSS F22 MA_DQS_H[1] F23 MA_DATA[15] F24 VSS F25 MA_DQS_L[2] F26 MA_DQS_H[2] F27 VSS F28 MA_DATA[24] F29 P_GFX_TXN[1] F3 MA_DQS_H[3] F30 VSS F31 MA_DATA[27] F32 MA_CHECK[0] F33 VSS F34 VSS F35 MB_CHECK[1] F36 VSS F37 MB_CHECK[0] F38 MB_DM[8] F39 VSS F4 P_GFX_RXN[0] F5 P_GFX_RXP[0] F6 VDDCR_SOC F7 DP1_TXP[2] F8 DP1_TXN[3] F9 P_GFX_TXP[3] G1 DP0_AUXP G10 DP1_AUXN G11 VDDCR_SOC G12 DP_BLON G13 VDDIO_MEM_S3_SENSE G14 VDDCR_SOC G15 TEST18 G16 RSVD G17 VDDCR_SOC G18 MA_DQS_L[0] G19 P_GFX_TXN[2] G2 MA_DATA[6] G20 VSS G21 MA_DATA[9] G22 MA_DQS_L[1] G23 VSS G24 MA_DATA[21] G25 MA_DM[2] G26 VSS G27 MA_DATA[18] G28 MA_DATA[29] G29 VDDCR_SOC G3 VSS G30 MA_DATA[31] G31 MA_CHECK[1] G32 VSS G33 MA_DM[8] G34 VSS G35 VSS G36 MB_DQS_L[8] G37 MB_DQS_H[8] G38 VSS G39 P_GFX_RXN[1] G4 P_GFX_RXP[1] G5 VDDCR_SOC G6 VSS G7 DP1_TXN[2] G8 VDDCR_SOC G9 P_GFX_TXN[3] H1 DP0_AUXN H10 VSS H11 DP_VARY_BL H12 DP_DIGON H13 VSS H14 PROCHOT_L H15 TEST19 H16 VSS H17 MA_DATA[4] H18 MA_DQS_H[0] H19 VDDCR_SOC H2 VSS H20 MA_DATA[3] H21 MA_DATA[8] H22 VSS H23 MA_DATA[14] H24 MA_DATA[20] H25 VSS H26 MA_DATA[23] H27 MA_DATA[19] H28 VSS H29 P_GFX_TXP[4] H3 MA_DM[3] H30 MA_DATA[26] H31 VSS H32 MA_DQS_L[8] H33 MA_DQS_H[8] H34 VSS H35 MB_CHECK[6] H36 MB_CHECK[7] H37 VSS H38 MB_CHECK[2] H39 VSS H4 VSS H5 P_GFX_RXN[2] H6 P_GFX_RXP[2] H7 VSS H8 DP0_HPD H9 VSS J1 VDDCR_SOC J10 VSS J11 VDDCR_SOC J12 VSS J13 VDDCR_SOC J14 VSS J15 VDDCR_SOC J16 VSS J17 MA_DATA[1] J18 VSS J19 P_GFX_TXP[5] J2 MA_DATA[2] J20 MA_DATA[13] J21 VSS J22 MA_DM[1] J23 MA_DATA[11] J24 VSS J25 MA_DATA[16] J26 MA_DATA[17] J27 VSS J28 MA_DATA[28] J29 P_GFX_TXN[4] J3 MA_DATA[25] J30 VSS J31 MA_CHECK[6] J32 MA_CHECK[7] J33 VSS J34 VSS J35 RSVD J36 VSS J37 RSVD J38 MB_CHECK[3] J39 VSS J4 P_GFX_RXN[3] J5 P_GFX_RXP[3] J6 VDDCR_SOC J7 VSS J8 VSS J9 P_GFX_TXP[6] K1 VSS K10 VDDCR_SOC K11 VSS K12 VDDCR_SOC K13 DP_STEREOSYNC K14 VDDCR_SOC K15 VSS K18 MA_DM[0] K19 P_GFX_TXN[5] K2 VSS K20 VSS K21 VSS K22 VSS K23 VSS K26 VSS K27 VSS K28 VSS K29 VDDCR_SOC K3 VSS K30 MA_CHECK[2] K31 MA_CHECK[3] K32 VSS K33 RSVD K34 MB_RESET_L K35 VDDIO_MEM_S3 K36 MB0_CKE[1] K37 RSVD K38 VDDIO_MEM_S3 K39 P_GFX_RXN[5] K4 P_GFX_RXP[5] K5 VDDCR_SOC K6 P_GFX_RXN[4] K7 P_GFX_RXP[4] K8 VDDCR_SOC K9 P_GFX_TXN[6] L1 VDDCR_SOC L10 VSS L11 VDDCR_SOC L12 VSS L13 VDDCR_SOC L14 VSS L15 VDDCR_SOC L16 VSS L17 VDDCR_SOC L18 VSS L19 VDDCR_SOC L2 VDDCR_SOC L20 VSS L21 VDDCR_SOC L22 TEST4 L23 VDDCR_SOC L24 VSS L25 VDDCR_SOC L26 VSS L27 VSS L28 VSS L29 P_GFX_TXP[7] L3 VSS L30 VSS L31 VDDIO_MEM_S3 L32 MA_RESET_L L33 MA1_CKE[1] L34 VDDIO_MEM_S3 L35 MB1_CKE[1] L36 MB0_CKE[0] L37 VDDIO_MEM_S3 L38 MB1_CKE[0] L39 VSS L4 VSS L5 P_GFX_RXN[6] L6 P_GFX_RXP[6] L7 VSS L8 VSS L9 VSS M1 VSS M10 VDDCR_SOC M11 VSS M12 VDDCR_SOC M13 VSS M14 VDDCR_SOC M15 VSS M16 VDDCR_SOC M17 VSS M18 VDDCR_SOC M19 P_GFX_TXP[8] M2 VSS M20 VDDCR_SOC M21 TEST5 M22 VDDCR_SOC M23 VSS M24 VDDCR_SOC M25 VSS M26 VSS M27 VSS M28 VDDIO_MEM_S3 M29 P_GFX_TXN[7] M3 MA0_CKE[1] M30 VDDIO_MEM_S3 M31 MA0_CKE[0] M32 MA1_CKE[0] M33 VDDIO_MEM_S3 M34 MA_ACT_L M35 MB_BG[0] M36 VDDIO_MEM_S3 M37 MB_ACT_L M38 MB_BG[1] M39 VSS M4 P_GFX_RXN[7] M5 P_GFX_RXP[7] M6 VDDCR_CPU M7 VSS M8 VDDCR_SOC M9 P_GFX_TXP[9] N1 VDDCR_SOC N10 VSS N11 VDDCR_SOC N12 VSS N13 VDDCR_SOC N14 VSS N15 VDDCR_SOC N16 VSS N17 VDDCR_SOC N18 VSS N19 P_GFX_TXN[8] N2 VDDCR_SOC N20 VSS N21 VDDCR_SOC N22 VSS N23 VDDCR_SOC N24 VSS N25 VDDCR_SOC N26 VSS N27 VDDIO_MEM_S3 N28 VSS N29 VDDCR_CPU N3 VDDIO_MEM_S3 N30 MA_BG[0] N31 MA_BG[1] N32 VDDIO_MEM_S3 N33 MA_ALERT_L N34 MA_ADD[12] N35 VDDIO_MEM_S3 N36 MB_ALERT_L N37 MB_ADD[12] N38 VDDIO_MEM_S3 N39 P_GFX_RXN[9] N4 P_GFX_RXP[9] N5 VDDCR_CPU N6 P_GFX_RXN[8] N7 P_GFX_RXP[8] N8 VSS N9 P_GFX_TXN[9] P1 VSS P10 VDDCR_SOC P11 VSS P12 VDDCR_SOC P13 VDDCR_CPU P2 VDDIO_MEM_S3 P27 TEST47 P28 VDDIO_MEM_S3 P29 P_GFX_TXP[10] P3 MA_ADD[8] P30 MA_ADD[9] P31 VDDIO_MEM_S3 P32 MA_ADD[11] P33 MA_ADD[7] P34 VDDIO_MEM_S3 P35 MB_ADD[9] P36 MB_ADD[11] P37 VDDIO_MEM_S3 P38 MB_ADD[7] P39 VSS P4 VSS P5 P_GFX_RXN[10] P6 P_GFX_RXP[10] P7 VSS P8 VDDCR_SOC P9 VSS R1 VDDCR_SOC R10 VSS R11 VDDCR_SOC R12 VSS R13 P_GFX_TXP[11] R2 VSS R27 VDDIO_MEM_S3 R28 VSS R29 P_GFX_TXN[10] R3 MA_ADD[4] R30 VDDIO_MEM_S3 R31 MA_ADD[6] R32 MA_ADD[5] R33 VDDIO_MEM_S3 R34 RSVD R35 MB_ADD[6] R36 VDDIO_MEM_S3 R37 MB_ADD[8] R38 MB_ADD[5] R39 VSS R4 P_GFX_RXN[11] R5 P_GFX_RXP[11] R6 VDDCR_CPU R7 VSS R8 VSS R9 P_GFX_TXP[12] T1 VSS T10 VDDCR_SOC T11 VSS T12 VDDCR_SOC T13 P_GFX_TXN[11] T2 VDDIO_MEM_S3 T27 VSS T28 VDDIO_MEM_S3 T29 VDDCR_CPU T3 VSS T30 MA_ADD[3] T31 MA_ADD[1] T32 VDDIO_MEM_S3 T33 MA_CLK_H[0] T34 MA_ADD[2] T35 VDDIO_MEM_S3 T36 MB_ADD[4] T37 MB_ADD[3] T38 VDDIO_MEM_S3 T39 P_GFX_RXP[13] T4 P_GFX_RXN[13] T5 VDDCR_CPU T6 P_GFX_RXN[12] T7 P_GFX_RXP[12] T8 VDDCR_CPU T9 P_GFX_TXN[12] U1 VDDCR_CPU U10 VSS U11 VDDCR_SOC U12 VSS U13 VDDCR_CPU U2 VSS U27 VDDIO_MEM_S3 U28 VSS U29 P_GFX_TXP[13] U3 VDDIO_MEM_S3 U30 VSS U31 VDDIO_MEM_S3 U32 MA_CLK_H[1] U33 MA_CLK_L[0] U34 VDDIO_MEM_S3 U35 MB_ADD[1] U36 MB_ADD[2] U37 VDDIO_MEM_S3 U38 MB_CLK_H[0] U39 VSS U4 VSS U5 P_GFX_RXN[14] U6 P_GFX_RXP[14] U7 VSS U8 VSS U9 VSS V1 VSS V10 VDDCR_CPU V11 VSS V12 VDDCR_SOC V13 P_GFX_TXP[14] V2 VDDIO_MEM_S3 V27 VSS V28 VDDIO_MEM_S3 V29 P_GFX_TXN[13] V3 VSS V30 VDDIO_MEM_S3 V31 MA_CLK_H[3] V32 MA_CLK_L[1] V33 VDDIO_MEM_S3 V34 MA_CLK_H[2] V35 MA_CLK_L[2] V36 VDDIO_MEM_S3 V37 MB_CLK_H[1] V38 MB_CLK_L[0] V39 VSS V4 P_GFX_RXN[15] V5 P_GFX_RXP[15] V6 VSS V7 P0A_ZVSS V8 VDDCR_CPU V9 P_GFX_TXP[15] W1 VDDCR_CPU W10 VSS W11 VDDCR_CPU W12 VSS W13 P_GFX_TXN[14] W2 VSS W27 VDDIO_MEM_S3 W28 VSS W29 VDDCR_CPU W3 TEST40 W30 VSS W31 MA_CLK_L[3] W32 VDDIO_MEM_S3 W33 VDDIO_MEM_S3 W34 MA_EVENT_L W35 VDDIO_MEM_S3 W36 MB_CLK_H[2] W37 MB_CLK_L[1] W38 VDDIO_MEM_S3 W39 P_HUB_RXP[3] W4 P_HUB_RXN[3] W5 VDDCR_CPU W6 P_ZVSS W7 P_ZVDDP W8 VSS W9 P_GFX_TXN[15] Y1 VSS Y10 VDDCR_CPU Y11 VSS Y12 VDDCR_CPU Y13 VDDCR_CPU Y2 VDDIO_MEM_S3 Y27 VSS Y28 VDDIO_MEM_S3 Y29 USB_SS_0RXP Y3 VSS Y30 VDDIO_MEM_S3 Y31 VDDIO_MEM_S3 Y32 MA_PAROUT Y33 VDDIO_MEM_S3 Y35 MB_ZVDDIO_MEM_S3 Y36 MB_CLK_L[2] Y37 VDDIO_MEM_S3 Y38 MB_CLK_H[3] Y39 USB_SS_0RXN Y4 VSS Y5 P_HUB_RXP[2] Y6 P_HUB_RXN[2] Y7 VSS Y8 VDDCR_CPU Y9 MA_ZVSS AJ37 MA_ZVDDIO_MEM_S3 Y34 Thanks to the folks at [H]ardForums. AM4 pinout 1331 pin.
I explained its purpose using a graph and image. It’s possible the CPU can run without the pin depending on its function.
They said it functions flawlessly, yet slots 2 and 4 fail in dual channel mode. Or they claim it works perfectly for dual channel.
Likely motherboard data pin information. If it functions in single channel, that’s great. Usually when a pin fails, the CPU becomes useless. For multi-tasking, dual channel memory is beneficial. In gaming, there’s minimal FPS difference between single and dual channel. I suggest trying it out. The only possible issues are the CPU LED turning on and a no-post signal. Otherwise, it should work fine.
It's a good deal at $80, but if it doesn't work, you can still get a profit by selling it.
It's tough to get rid of damaged parts... that's your call. Personally, I'd check if AMD would replace it. Be honest with them. You own a CPU with a bad solder joint. It's not expensive for them, honestly.
That's what I'm saying to them. I'm hoping they'll reply soon. I've got a 2600x file, and these items are selling for about $100 on eBay, though they're often broken. That's not a big deal.
Yea I de-lidded mine. Since there is no market for de-lidded chips, I kept it instead of selling it. Do you think de-lidding AMD chips could become a market?