Teamgroup UD5-6000 A memory boost. Operating at DDR 6000MHz. Seeking reduced clock speeds instead of MHz.
Teamgroup UD5-6000 A memory boost. Operating at DDR 6000MHz. Seeking reduced clock speeds instead of MHz.
I have 32GB of Teamgroup UD5-6000 DDR5 RAM. My motherboard is an Asus X670-P Wi-Fi board. I'm using a FCLK speed of 2000 and keeping memory at 6000MHz. I aim for lower latency without going above 6000MHz. Current scores are around 69ms with AIDA64 benchmarks, which vary a lot. I want to know if I should tweak timings or voltage. I'm running at 1.35V and increasing tCL to 30 hurt latency in tests. Any advice?
Not as expected, the FCLK isn't linked to memory speed. Most CPUs should handle at least 2066MHz, with top models reaching 2200MHz. This suggests instability—tCL 30 might perform better, though not significantly. It seems you likely pasted Buildzoid's timing data. You could try setting tREFI around 50k instead of 65,535, which would provide some flexibility, though that’s probably the only timing I’d anticipate having room for.
Your system is performing well with a BIOS setting of 11677 and a memory speed of 6000MHz. For stability, aim for a clock frequency around 2066 MHz or higher. If you're currently at 67.9ms latency and passing OCCT tests, consider adjusting your timing parameters slightly lower—perhaps by 10-20% depending on the exact specs. Checking 32, 36, 36, 36, 28, and 64 MHz values can help identify the optimal setting. Let me know if you need further guidance.
TREFI is the setting you really need to optimize for better size. It represents how long it takes before memory becomes unavailable because of refreshing; the longer this interval, the better the performance. You can aim for at least 2066, and higher values are achievable with more work.
I adjusted the fclk to 2067 and set the tREFI to 50000. Latency improved to 65.3. To lower it further, increasing voltages to 1.4 and VDDP to 1.100 worked well. Current speeds are 87,702 read and 91,438 write from aida64. Trying CL30 or 28 with higher voltage might give better results. Timings are now 32, 36, 36, 28, 64—consider tweaking them if needed.
Increased the voltage to 1.4V and CL30 should function. CL28 remains uncertain, but with a particularly capable kit it could work (though CL30 didn't perform at 1.35V either). The primaries seem well-tuned with little room left. You might try a bit more FCLK adjustment if needed—it's likely the final adjustment.
CL30 functions properly with latency reduced to 64ns. Adjusting the FCLK to 2033 or 2067 offers better performance at 6000MHz RAM compared to using 2000 because it aligns more closely with the desired clock speed, minimizing timing issues and improving stability.
Adjusting fclk to 2067 helps synchronize your system more effectively when your RAM operates at 6000MHz. This change can improve timing stability and performance.