Processing units and memory architecture lanes
Processing units and memory architecture lanes
I'm trying to understand PCIE 3.0 lane speeds, especially 1x, 4x, 8x, and 16x. I can't find clear diagrams or charts online, so I'm looking for reliable info on their actual speeds. Sometimes results vary between 16 Gbps and 32 Gbps depending on conditions. Could you help clarify or share a good reference? Thanks!
Directly from Wikipedia: Version 3.x delivers 8 GT/s, 985 MB/s per lane, reaching 15.75 GB/s overall. Version 4.0 boosts to 16 GT/s, 1.97 GB/s per lane, totaling 31.5 GB/s. Scaling up to eight lanes, the performance jumps significantly.
It's crucial to understand that inserting a 3.0 x16 card into a 4.0 port with just 8 lanes will limit performance to 8 lanes operating at 3.0 speeds. This is because the physical constraints of the lanes determine the maximum throughput, regardless of how fast the devices are running.
Absolutely accurate. Or a 4.0 8x in a 3.0 x16 channel as seen with the AMD RX 6500 if I remember right.
That's why I mentioned each direction. I understand it's referred to as full duplex, while others might not. It's simpler to grasp. We don't have to calculate the combined send and receive to determine bandwidth limits. The PCI-E standard specifies the rate—about 1 GB/s per lane in each direction. It's straightforward and easy to comprehend. I'm a bit puzzled about how you can achieve 32 sends or 32 receives from that...