PCIe motherboard interfaces
PCIe motherboard interfaces
Hello, I'd like to understand how the various parts—like USB ports and PCIe slots—connect to the chipset and CPU. My interest started from a previous discussion. Could anyone explain this process? I want to grasp how these connections work, especially the PCIe lanes assigned to each device and their routing. Up until now, I've learned that the Gigabyte X570 Aorus Pro WiFi v1.0 (without Thunderbolt support) has 20 PCIe lanes: 4 go to the CPU, 4 to an x4 slot, 4 to an M2 slot, and 1 to a PCIe x1 slot. One lane connects to the Intel I211 Ethernet controller, another to the WiFi AX200, and so on. I'm unsure where the remaining 4 lanes end up—possibly converted into SATA ports. What's puzzling is the HWiNFO report I saw. It lists details like 8 lanes for the CPU, 4 for PCIe x4, 1 for the Ethernet controller, etc., but I can't find a clear explanation. The M2 slot and PCIe x1 slots aren't visible in the tool, suggesting no devices are plugged in there. This is confusing because AMD mentions the chipset has five x4 PCIe PHYs (totaling 20 lanes). I tried searching online for more details but couldn't locate a reliable source. Your guidance would be greatly appreciated. Best regards, Chiyawa. P.S.: I'm using HWiNFO 6.24-4120 DESKTOP-OB74C2F.CSV
I am by no means an expert on this topic, but here's a picture that might make a little more sense: If I understand it correctly, HWInfo doesn't make a distinction between lanes from the CPU and lanes from the chipset, which is why it adds up to more than it looks like it should. There are 24 total PCIe lanes from the CPU with 16 lanes for the graphics card, 4 for storage (m.2), and 4 for the chipset. The chipset then has 16 PCIe lanes that it uses for PCIe slots, m.2 slots, and SATA. If I said something wrong, someone feel free to correct me, because like I said I am no expert in this.
CPU supports 24 PCIe lanes: 16 designated for graphics, and one PCIe x16 port or two slots each with four lanes. Four lanes connect to the M.2 connector, while another four can be used for the M.2 NVMe interface or turned off to free up additional SATA ports. The chipset adds extra PCIe lanes, reaching up to 12 on X570 models, though as shown in the diagram only eight are actual lanes, with the remaining four available for slots, NVMe ports, or disabling them.
Well, actually it kinda does, as this is all in the AMD 500 series chipset. Here's the screenshot:
These components are fully integrated within the chipset, not accessible externally. There are no pins to connect PCI-e lanes to slots or M.2 connectors. It resembles the HSIO features found in Intel chipsets, allowing single or multiple HSIO links to link parts inside the chipset.
I understand. This... It sparks some interest. The reason behind the many PCIe lanes in a SATA controller isn’t clear—especially since they only handle two SATA ports. More importantly, are the HWiNFO reports accurate about the PCIe lane allocation? An article mentioned that the chipset offers 40 PCIe lanes. Here’s the link: https://www.techpowerup.com/255008/amd-x...-4-0-lanes This seems like the most reliable source I found, though it raises questions. We know the CPU gets four lanes, usable 16, leaving room for SATA and USB XHCI controllers—about twenty more lanes. Yet, even with that, high bandwidth isn’t always necessary. The chipset supports up to eight USB 3.2 Gen 2 ports (80Gbps total), four USB 2.0 ports (≈2Gbps), and four SATA ports (24Gbps), totaling around 106Gbps. PCIe Gen 4 x16 delivers 252.06Gbps, while x8 gives 126Gbps. HWiNFO claims it’s using Gen4 PCIe, but that conflicts with the reported usage. I’m curious to explore further and avoid making mistakes. *Assuming the standard X570 setup*
The 40 PCIe lanes were likely mixed up. Some people combined the PCIe lanes from the CPU with those from the chipset, resulting in 40 total. Processors generate several PCIe lanes—up to 24 for AM4 sockets. Four of these are reserved for connecting the chipset to the processor, leaving 20 PCIe lanes available for other uses. Out of those, 16 are intended for video graphics (X16), potentially split into two 8-port slots depending on the chipset model; B450 models can handle it, x470 and x570 can, while B550 probably can't. The remaining four lanes are usually allocated to the first M.2 connector, though this depends on the motherboard maker. Imagine the chipset as a network hub with 24–48 gigabit ports and a high-speed port for external access (WAN). The high-speed port corresponds to the PCIe X4 link to the CPU, which is fixed. Inside the chipset, it manages this X4 connection (up to about 4 GB/s each way) and includes a PCIe controller that can produce roughly 24–32 lanes, but only 8–12 are exposed outside the chipset. For SATA, it's reasonable to assume they use four PCIe lanes per group of four connectors. The top bandwidth for a single SATA port is around 560 MB/s. Remember they licensed SATA and USB controllers from Asmedia, likely using PCIe 3.0 only inside the chipset. This suggests each PCIe lane inside the chipset supports up to about 970 MB/s (around 950 MB/s after overhead). A single SATA port maxes out at 560 MB/s, so most dual-port controllers share one lane each. If a port is busy, it can reach 560 MB/s; using two ports simultaneously yields roughly 450 MB/s per port. The diagram shows multiple SATA controllers in the X570 chipset, each with four ports, indicating a need for at least two PCIe lanes to handle the load. It seems the confusion comes from misinterpreting how lanes are allocated across components.
It seems like you're trying to piece together some information about a chipset. Without more context, it's hard to give a precise answer, but generally, understanding these connections can be tricky. If AMD doesn't share technical details, it's hard to verify reports. You might need to work closely with motherboard manufacturers for full insights. Thanks for reaching out!
I tried to organize everything I learned about the PCIe lane distribution in the Gigabyte X570 Aorus Pro WiFi. It looks like they allocated 4 lanes for the PCIe x4 slot, 4 for the M2 slot, and 2 for the PCIe x1 slot—each lane assigned to a specific component. The Ethernet controller gets one lane, WiFi gets another, and two lanes are converted into SATA ports. Overall, there are 14 lanes in use. It seems some of their testing methods might need adjustments. Regarding the USB setup, I figured out that there are likely two USB XHCI controllers handling all USB ports. From the image I shared earlier, there are 8 USB 3.2 ports and 4 USB 2.0 ports. It appears the four USB 2.0 ports could be disabled since they use a hub instead of direct connections. The layout includes one USB-C on the back panel, one USB 3.2 Gen 2 on the back panel, four USB 3.2 Gen 1 headers at the back panel, and several USB 3.2 Gen 1 ports converted to USB 2.0. One of these is dedicated to Bluetooth. Still, it’s a bit confusing how everything fits together.