No, Command Rate IMC and DIMM are not bound.
No, Command Rate IMC and DIMM are not bound.
I assembled an E5 2640 V3 with three 8GB Netac DDR4 1600MHz modules (actual clock) using triple-channel on a Huananzhi X99-TF processor. Many users report running this CPU with memory at 1T, while my setting is 3T—no BIOS tweak seems possible without risking instability. Could this be due to an IMC issue or faulty memory? To confirm, I’ll share the CPU-Z data for both components. In a related review of the E5 2666 V3, I noticed significantly lower memory bandwidth than expected, with Command Rate being the slowest parameter. I’m thinking about upgrading to an E5 2666 V3 for extra cores, increasing the clock by 100MHz and boosting memory speed from 1066.5MHz to 933MHz (DDR3 on DDR4). I’m also exploring whether the IMC problem might be the cause. Before making changes, I didn’t verify the BIOS settings; I didn’t adjust single-thread clock boost after updating. I’ll try flashing the BIOS without IMC undervolting in a few days since I can’t do it right now.
Before offering any details, we should check the SPD tab of the memory. It will ask the board to execute 3T if that’s the intended configuration.
It looks like the problem could be related to the memory's specifications. I attempted a retraining and cleared a few DIMMs, but it returned to 3T.
I just reviewed the matter further and checked the SPD CPU-Z page. None of the images showed the Command Rate value, which suggests it's managed by the IMC only, and memory isn't affected since it's not listed in the profile table. I searched for more explanations about CR and found some alignment with this idea. I plan to reset the IMC voltage and see if it maintains 2T, or at least try the E5 2666 V3 if that helps.