New initiative/software for assessing core-to-core delays
New initiative/software for assessing core-to-core delays
The main point is AMD's latency remains quite poor for their chiplets. Intel performs similarly across various sockets, whereas AMD uses a die within the same package. This matters because it affects how loads are managed. If you use core-aware scheduling, you avoid splitting tasks between different NUMA domains. However, when running virtual machines with customers, treating the chip as a large pool of cores isn't feasible. It will be worth watching Intel's future 3 compute 1 IO approach compared to Epyc.
The creator behind the tool is employed at Two Sigma, an algorithmic investment company. Fast trading strategies highlight how even tiny delays can matter when handling complex calculations across many cores. This field shows that optimizing core setup and cache speeds can really impact performance. I’m interested in the Apple M1 Ultra and its innovative interconnect design that lets two M1 Max chips connect seamlessly. How does this compare to AMD’s CCX architecture, especially given TSMC’s involvement for both companies? Anyone up for testing it on an M1 Ultra?