LPDDR5 6400
LPDDR5 6400
Hey, your observation makes sense. The 786.5Mhz figure in HWINFO64 likely reflects the memory clock speed, which you confirmed via CPU-z showing FSB/uncore at 1:8. That suggests the intended clock speed would be around 6400Mhz. With a 6800U mini PC, it should handle light tasks like browsing and music playback smoothly, and dual-booting with OMV could give you a solid NAS experience.
DDR supports double data rate, meaning the output speed should be twice the read rate. Your FSB speed is 1:16, and with a 3200 MHz memory, it makes sense that the actual speed won’t exceed 6400 MHz. CPU-Z and HWINFO64 are displaying this for DDR4. Could you share some of your own screenshots?
It seems like your RAM is acting up, but the BIOS says it's working at 6400 MHz. That doesn't help clarify the issue.
I discovered these details about the updated clocking design for better timing control. Previously, the C/A clock matched data-strobe rates across LPDDR standards, but this new approach increases demands on both DRAM lanes and SoC timing alignment. The controller in the SoC usually operates at half the clock speed of the CK, especially during DDR PHY Interface mode. For instance, with a 4267 Mbps LPDDR4/4X, CK runs at 2133 MHz, DQS at 1066 MHz, and C/A at 2133 Mbps. This setup struggles to scale to LPDDR5 speeds. To address this, LPDDR5 uses a different strategy: CK frequency drops to a quarter of the data-strobe rate for speeds over 3200 Mbps, and halves it below that threshold. This adjustment lets C/A run slower—down to 1600 Mbps—while still allowing transitions at both rising and falling edges, improving timing margins. A slower CK also lets the SoC handle timing more efficiently and boosts performance since controllers can run at 800 MHz in DFI 1:1 mode. Unlike older designs that used bidirectional strobes, LPDDR5 introduces single-direction strobes for writes (WCK) and optional reads (RDQS). At lower speeds, power savings are possible by skipping the dual strobe, but higher speeds require a differential strobe setup. This evolution ensures better scalability and efficiency.