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kenneth270
Junior Member
49
08-08-2016, 09:28 AM
#1
We've discussed Zen6 before and it's rumored to run on RDNA3.5 rather than RDNA4. Recent leaks from sources like [hothardware](https://hothardware.com/news/amd-zen6-ry...tails-leak) and [wccftech](https://wccftech.com/amd-next-gen-ryzen-...-l3-cache/) indicate more details. These suggest possible chiplet designs supporting up to 12 Zen6 or 16 Zen6c cores, with enhanced L3 cache on Zen6 versions. The AMD Zen6 AM5 CPUs could reach 24 or even 32 cores, paired with significantly larger L3 die caches. This setup would likely combine compact Zen6 cores with X3D cache, possibly using I/O chiplets and a major redesign of memory interfaces. Expect AMD to introduce new silicon bridges for faster communication between chiplets, possibly integrating advanced caching and memory controllers. APUs are expected to lag behind CPUs, with no plans for X3D cache layers on iGPUs. AMD appears to be planning a major refresh around mid-2025, with chips possibly available by 2026.
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kenneth270
08-08-2016, 09:28 AM #1

We've discussed Zen6 before and it's rumored to run on RDNA3.5 rather than RDNA4. Recent leaks from sources like [hothardware](https://hothardware.com/news/amd-zen6-ry...tails-leak) and [wccftech](https://wccftech.com/amd-next-gen-ryzen-...-l3-cache/) indicate more details. These suggest possible chiplet designs supporting up to 12 Zen6 or 16 Zen6c cores, with enhanced L3 cache on Zen6 versions. The AMD Zen6 AM5 CPUs could reach 24 or even 32 cores, paired with significantly larger L3 die caches. This setup would likely combine compact Zen6 cores with X3D cache, possibly using I/O chiplets and a major redesign of memory interfaces. Expect AMD to introduce new silicon bridges for faster communication between chiplets, possibly integrating advanced caching and memory controllers. APUs are expected to lag behind CPUs, with no plans for X3D cache layers on iGPUs. AMD appears to be planning a major refresh around mid-2025, with chips possibly available by 2026.

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tara49107
Junior Member
18
08-11-2016, 10:47 PM
#2
Expect a similar two-year pattern as seen since Zen5 was introduced. Likely 12-core CCDs will appear, though not the compact "C" cores we see. It’s unlikely these will reach consumer devices outside of APUs (such as Ryzen 8000). Most details have been circulating for a few weeks but won’t be widely available soon.
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tara49107
08-11-2016, 10:47 PM #2

Expect a similar two-year pattern as seen since Zen5 was introduced. Likely 12-core CCDs will appear, though not the compact "C" cores we see. It’s unlikely these will reach consumer devices outside of APUs (such as Ryzen 8000). Most details have been circulating for a few weeks but won’t be widely available soon.

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KinqPaiiN
Junior Member
14
08-12-2016, 03:17 AM
#3
Could be a drawback? Adding an X3D cache slice might complicate things and reduce performance if not managed well.
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KinqPaiiN
08-12-2016, 03:17 AM #3

Could be a drawback? Adding an X3D cache slice might complicate things and reduce performance if not managed well.

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3Edge
Senior Member
718
08-12-2016, 06:13 AM
#4
He probably intended that Zen 6c won't make it into common CPUs.
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3Edge
08-12-2016, 06:13 AM #4

He probably intended that Zen 6c won't make it into common CPUs.

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Cutie_Kitcat
Senior Member
644
08-12-2016, 06:56 AM
#5
The c-cores operate at reduced power, which means a slight drop in clock speed compared to regular cores. On desktops, performance matters more, but on mobile devices, power usage becomes crucial.
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Cutie_Kitcat
08-12-2016, 06:56 AM #5

The c-cores operate at reduced power, which means a slight drop in clock speed compared to regular cores. On desktops, performance matters more, but on mobile devices, power usage becomes crucial.

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superdjpvp
Member
51
08-12-2016, 07:33 AM
#6
Currently. But what would be the reason to have them as lower-power if there is plenty of X3D cache that they could have beneath ? To me it looks like win-win. They could get rid of all L3 and have just an X3D with plenty more cores on the top die.
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superdjpvp
08-12-2016, 07:33 AM #6

Currently. But what would be the reason to have them as lower-power if there is plenty of X3D cache that they could have beneath ? To me it looks like win-win. They could get rid of all L3 and have just an X3D with plenty more cores on the top die.

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LOLboy311
Member
114
08-12-2016, 08:03 AM
#7
AMD is likely to adopt similar strategies in the future. Because cache performance doesn't improve much with smaller nodes, they may eventually relocate the L3 cache to a completely separate die. This change seems improbable for Zen 6, as the design was established long ago—by now it's too late to implement such a major shift. A more advanced version like Zen 7 or 8 might follow, but Zen 6 isn't moving forward in this direction.
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LOLboy311
08-12-2016, 08:03 AM #7

AMD is likely to adopt similar strategies in the future. Because cache performance doesn't improve much with smaller nodes, they may eventually relocate the L3 cache to a completely separate die. This change seems improbable for Zen 6, as the design was established long ago—by now it's too late to implement such a major shift. A more advanced version like Zen 7 or 8 might follow, but Zen 6 isn't moving forward in this direction.