It appears most current Intel CPUs are limited to 20 lanes, but your setup may not meet that requirement.
It appears most current Intel CPUs are limited to 20 lanes, but your setup may not meet that requirement.
The chipset lanes originate separately from the CPU. They function independently. However, the chipset (and any devices linked to it) and the CPU are linked through just four lanes, meaning heavy usage on the chipset could cause performance limits.
The absence of lanes prompted my decision to use a TR 2950x. I'm now using three SSDs, mainly swapping from 2x2TB to a larger 3.84TB drive. Some X670E boards support five drives, but the costs were very high. Performance dropped noticeably after switching to a 3900x, though it's nearly twice as fast as a 2950x with a consumer AM5 CPU now. I'm not too worried about sharing lanes much, since most of my use is for capacity. Transfer speeds remain solid at around 1.5GB/s. I might replace the other two 2TB drives eventually.
PCIe functions as a communication pathway, allowing all connected devices to utilize the available speed without CPU involvement. The limitation arises when attempting to connect several devices with more than four data channels, causing performance to stall at the four primary connections.
It depends on your setup. The CPU lanes you have are separate from the chipset slots. If you have extra slots available, you can still use them without affecting your bandwidth, as long as the chipset supports it. Just check your motherboard documentation to confirm compatibility.
Ensure no peripherals are connected to the PCIe bus for compatibility.
The CPU features 20 PCIe lanes, though their allocation differs between motherboards. Generally, 16 lanes are reserved for the GPU, with 4 dedicated to one of the M.2 slots, ensuring full bandwidth availability for those connections. The chipset links to the CPU through the DMI bus; the Z790 supports an 8x DMI connection, but this can vary by chipset. This adds to the 20 PCIe lanes available. All devices linked to the chipset share the DMI bus bandwidth dynamically—transferring data to multiple devices at once may slow performance temporarily, though each device will still operate at its maximum speed. In practice, this behavior won’t cause significant issues.