Intel processors utilize minimal cache memory.
Intel processors utilize minimal cache memory.
Recently I was evaluating my CPU against a friend’s i9 9600K and his i5 3600, wondering why mine has 35MB cache while his has 9.5MB. I also noticed that Ryzen processors usually come with significantly more cache compared to Intel chips.
Since AMD could and chose to, they increased the cache capacity. Cache sizes shrink in budget models—often because of design choices (like removing a CCX also eliminates the cache on Ryzen)—or simply to differentiate products. Mostly Intel does this to make i7 and i9 seem quicker in tasks that rely heavily on cache.
It seems performance depends on balancing factors. I recall Ryzen's RAM latency is generally higher than Intel's, and this might affect cache behavior as well. The question is whether slower cache operations require additional compensation.
The way you count it matters too. Don't add it all up, unless you know you can. Mainstream Intel CPUs historically had an inclusive cache. Whatever is in L2 is also in L3. So you just look at the L3 as indicator. The 9600KF has 9MB, or 1.5MB/core. It is easier to look at them per-core as generally Intel gives you 1.5MB/core on i5, 2MB/core on i7 and above, and some historic Xeons have 2.5MB/core. There are exceptions so don't take that as a hard rule, but it is often the case. For example, Broadwell on desktop only had 1MB/core of L3, but it had a 128MB L4 cache, which was unusual. With Zen 2, AMD went large at 16MB of L3/CCX. Here we don't look at it per-core so much as per-CCX, since that is the more logical unit. I don't think AMD changed from recent history, and they run an exclusive cache. That means data in L2 doesn't get duplicated in L3, thus you can count them both for best case effective total cache. In practice, the L3 is so much bigger than the total L2, the L2 isn't really significant and may be ignored for simplicity. Note AMD only started going large with Zen 2. Older Ryzen was still closer to 2MB/core than 4MB/core (assuming a fully loaded CCX, since the effective cache/core goes up if they disable more cores). Oh, one more factor which isn't obvious. Intel's CPU cache is unified. Any core can reach any part of the L3 cache with only a small difference in latency depending on how far around the ring it has to go. On Ryzen, each CCX is isolated from each other. If it isn't local, you take a big penalty to go outside. Rumours are Zen 3 will go to a bigger CCX which will help that a lot.