Exploring the concept of infinity fabric involves delving into its theoretical aspects and implications.
Exploring the concept of infinity fabric involves delving into its theoretical aspects and implications.
My perception is that Ryzen 2 had a strict cap on infinity fabric performance, setting a practical upper bound despite not being an absolute barrier. At 3733 MHz, the fabric would automatically adjust to X2 speed, causing real-world memory speeds around 3600 MHz or higher to drop. Recent builds using 4000 and 4400 MHz RAM could fall into this range. Is there a way to shift this threshold? Adjusting timing could let it run faster without sacrificing too much speed, but lowering the clock might help. Is there a baseline CAS level below which performance issues become noticeable? Edited June 12, 2020 by Bombastinator Ihateautocorrect
I’ll gladly clarify the interconnect topic you mentioned. The key points involve the IMC and FCLK. Setting memory to a 100:100 ratio generally improves interconnect performance at higher frequencies. Are you referring to the FCLK specifically? It depends—IMC might be adjusted or the SOC voltage raised, effectively overclocking the IMC. If you have four channels, bandwidth becomes distributed across two channels, which increases stress on the interconnect and forces it to move data faster, thus increasing FCLK demand. The FCLK has fixed limits; you can’t change it, though latency is more flexible. This explanation is a rough summary. I’m busy with other things, so I’m not fully focused right now.
Note: A memory or CPU overclock could impact either one if the interconnect encounters issues.
Edit: June 12, 2020 – TofuHaroto
I'm not sure about those terms. It seems like some research is necessary. "Infinity fabric" felt like a marketing shorthand, possibly misleading. It might refer to a situation where performance is limited by certain constraints—like a small boost that doesn't fully utilize the system or a switch that can't be changed without issues. I don't fully grasp what it means, and I'm not confident in this explanation. It seems I need to clarify these ideas before understanding them better.
When I first learned about it, I wasn't sure what it was, but it involves the interconnect F clock which technically refers to the speed at which data moves between chips. The imc handles the memory controller. Edit: trc essentially describes how long the CPU can read from or write to the DRAM. Edited June 12, 2020 by TofuHaroto
I understand the integrated memory controller and how it simplifies things. Thanks!