Configuration Details
Configuration Details
These aren't the adjustments you mentioned needing changes—they usually don’t train anything below 6400 unless you're under 6400. The ones I referenced are the timing details for tRDRD_sg_Runtime and tRDRD_sg_Runtime, which tend to work well at 16/8 and noticeably impact bandwidth. The same applies to tWRWR_sg/dg, expected to run at 12/8. All these voltages are optimal, though you can safely increase them if you wish. Higher isn’t always better. There’s at least one BIOS setting on my Unify-X where raising VDDQ above 1.3V prevents VST at 7800, while the board defaults to 1.45V for another reason. Just because you have some margin doesn’t mean that’s the margin I’m emphasizing.
Based on my experience, this should work with every Hynix-based kit.
I wanted to share an update. 1usmus appears quite straightforward to pass. After launching VST, I had to establish an entirely new setup and discard my old Excel spreadsheet. Here’s where I stand now, attached for reference. I’m uncertain about the best starting point. From what we observe, 1.48 and 1.50 successfully passed VST testing. 1.49 remained untested since 1.48 worked. I’m not clear on the next steps for adjusting any of these voltages. I plan to begin by lowering the IRV and MC v, identifying the failure point. Once that’s done, I’ll reduce one at a time to determine if both require higher voltages. After that, we can adjust the RAM voltages. Unless you have a better idea, good luck!
Observe that VDDQ TX and VDD2 (IVR and MC as official names from Intel, I'll use them consistently) don't need identical values and often prefer different ones. If you aim to reduce them, try adjusting them individually rather than changing both together at once. VDDQ tends to settle near 1.35V, whereas VDD2 usually stays around 1.45–1.5V, so begin with VDDQ first.