Concerns about PCIe x4 bandwidth consumption
Concerns about PCIe x4 bandwidth consumption
The PCIe lanes control bandwidth by sharing the available data flow, adjusting speed based on demand. With multiple devices competing for the same lanes, the system dynamically manages usage rather than locking a fixed limit. Adding an Intel Arc encoder would increase the load, but it wouldn’t necessarily cap performance unless the total demand exceeds the combined capacity. The chipset would likely prioritize the PCIe slot if throughput surpasses certain thresholds, though it can’t guarantee priority over all devices. Buffering depends on the encoder’s capabilities and your system’s handling, not a fixed rule.
The X570 chipset links to the CPU via a PCI-E 4.0 x4 interface, offering roughly 7.5 GB/s of data transfer. The M2A_CPU connects directly to the CPU using four PCI-E lanes, which explains why it's not uncommon to utilize them. Linking the Samsung 980 Pro to that M.2 slot makes sense given its four lanes, leaving the remaining lanes available for other uses. View the chipset layout in the manual; it features four fixed SATA ports, eight PCI-E lanes, and two modular sections that can switch between four lanes or SATA ports. On the motherboard, it appears configured as follows: four of the eight PCI-E lanes go to the M.2 Wi-Fi card, another four connect to a 2.5G Ethernet port, and two of the eight lanes serve USB 3.2 at 20 GB/s. Four lanes remain for M2C_SB or a PCI-E slot, and the remaining four can be assigned to M2D_SB or additional SATA ports. When handling the two select options, one is set to four lanes for M2B_SB and the other offers a choice between four lanes for M2D_SB or extra SATA ports. All of these are funneled through the PCI-E 4.0 connection to the CPU (~7.5 GB/s). Adding an ARC video card in that slot would block the M2C_SB port, as they share the same lanes. Regarding performance impacts, OBS would capture frames and send them via PCI-E to ARC, making bandwidth usage dependent on resolution and frame rate. For example, at 1440p at 60 fps, you'd see roughly 420 MB/s of data moving between CPU and video card—about half the bandwidth of a PCI-E 3.0 x1 lane.
I’m working with that direct CPU PCIe link, but I didn’t mark it as using the 4.0 x4 bandwidth that the chipset limits. I’m also skipping the Wi-Fi module because I’m relying on the LAN connection. I’m thinking about a scenario where one drive sends a sudden burst of 7GB, leaving only about 870MB/s available at that time. If the encoder receives more than that amount, would it cause frame drops? I assume it would need to buffer incoming data or maintain a steady flow to keep things running smoothly. Thanks for the thorough analysis.
It’s the Gigabyte Radeon RX 6800 GAMING OC 16G model that occupies three slots just by being there. I’m leaning toward the A310 or A40 after reviewing everything and considering the advice from helpful users. If it’s in the x8 slot, I’d like to see how it fits physically and handles heat. I’m mainly curious about the bandwidth issue and would appreciate someone’s insight.
Mellenius highlighted the issue on the Gamers Nexus Discord. For this motherboard, it divides the 4.0 x4 into two 3.0 x4 sections. Just one M.2 slot shares the same 3.0 bus with the PCIe x4 port, so it would be either the M.2 slot or the x4 slot. This suggests I’d struggle to significantly reduce bandwidth in the x4 lane.