Boost clock operates by amplifying the signal to improve timing accuracy.
Boost clock operates by amplifying the signal to improve timing accuracy.
I recently upgraded from a 1060 to a 2070 super. I didn’t have enough funds for a 3080 or 3070, so I found a solid second-hand deal on a 2070 super. The challenge is my i5 7600k paired with an H170 chipset. I also secured a decent used deal on the 7600k itself. Previously, I ran an i5-6500 for years but spent about 30€ to upgrade to a 7600k. The jump from 7600k to higher speeds is surprising, as it’s a single-core processor. It’s still handling most games well, but performance feels limited. I’m trying to improve it further. The problem I noticed is its clock speed: it’s stuck around 3997MHz and uses around 40 watts. Because it’s water-cooled, it stays cool but doesn’t reach higher frequencies. I’m curious why it doesn’t push further, given the potential. More details: I’m using an Asrock H170 Pro4 motherboard. Temperatures and clock readings were tracked with HWmonitor. Stress tests included Aida 64, p95, Rainbow 6 Siege, and Counter-Strike.
It makes sense, considering the efficiency and design. At lower loads, only 40 watts are needed to maintain performance.
The power consumption varies with the load, and games usually aren't the biggest energy consumers. That figure looks accurate.
Base clock determines the target frequency if turbo is turned off and Intel confirms it can sustain TDP at that speed. Turbo represents the maximum boost possible while ignoring TDP limits. Keep in mind the upper turbo cap varies with workload—only reaching 4.2GHz when the CPU is lightly active, and 4GHz for all-core boost.
Is it getting power? It might be operating at a very low voltage. Even full usage doesn’t guarantee a heavy workload. Alternatively, the sensor could be faulty, which is possible too.
I'm running p95 small fft now. It's providing a more accurate wattage, around 57 package. 1.195v. It looks like this is the full performance I'll get :C.
TDP does not match the actual chip power usage even though the chip should consume more than TDP. Different instructions require varying amounts of power.
power is frequently much below the maximum design power for these lower-power components.