Area for HT/SMT components, future perspectives extended
Area for HT/SMT components, future perspectives extended
Considering the recent security issues, I began questioning whether HT or SMT would no longer be relevant. While SMT isn't directly affected, I'm assessing the industry's possible direction. The key points are: implementing HT/SMT incurs costs like increased die size and power consumption. Do the performance benefits justify these expenses? If cores become abundant, do we still require extra threads? Absent HT/SMT, critical path threads sharing cores with less vital code would be less likely to slow things down. Consistent performance seems more valuable than peak speed, though peak performance may still exist in certain processors. I'm observing a trend toward more cores, especially with AMD leading the way. Some applications scale well, while others struggle due to architectural constraints. The challenge lies in determining whether the added complexity of HT/SMT remains necessary or if it's becoming obsolete. References from the P4 era suggest a 5% die area increase, which is modest compared to gains. However, since CPU designs have evolved significantly, it's unclear if that figure holds today. The complexity of new features might require even more intricate HT/SMT solutions, making the trade-off harder to evaluate. I'm seeking clearer data on actual die area usage and performance metrics to make a more informed judgment.
requires adjustments to the FPU and pipeline prior to and following the CPU. edit: this must be integrated into the design and architecture.
It isn't free; you need to build it in silicon if you want it. Certain sections must be repeated to ensure that additional thread. Parallel multi-threading is possible. You can interpret this as AMD's version of HT, or the general term for what HT represents.
It seems the idea was simply embedded in the CPU's instructions, not a physical component.