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7800x3d to 9800x3d latency and performance impact

7800x3d to 9800x3d latency and performance impact

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jsdoyle
Member
77
10-11-2023, 10:22 PM
#1
Hello, I'm curious about how the gaming performance of 7800x3d/9800x3d relates to RAM timings, especially regarding CAS latency. From what I know, improvements beyond 6000/6400Mhz seem limited in terms of frequency. Concerning CL speeds, switching from CL30 to CL26 might affect performance noticeably at average or low frequencies.
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jsdoyle
10-11-2023, 10:22 PM #1

Hello, I'm curious about how the gaming performance of 7800x3d/9800x3d relates to RAM timings, especially regarding CAS latency. From what I know, improvements beyond 6000/6400Mhz seem limited in terms of frequency. Concerning CL speeds, switching from CL30 to CL26 might affect performance noticeably at average or low frequencies.

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Reuben135
Member
89
10-12-2023, 06:58 AM
#2
The cost of CL26 remains excessive, and many CL30 sets (especially those relying solely on SK Hynix DRAM like G.Skill Flare X5) can still drop to C28-27 with your own overclocking. Even without that, CL30 remains ideal for productivity and gaming stability, offering better performance than a C40-36 kit while delivering a superior experience.
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Reuben135
10-12-2023, 06:58 AM #2

The cost of CL26 remains excessive, and many CL30 sets (especially those relying solely on SK Hynix DRAM like G.Skill Flare X5) can still drop to C28-27 with your own overclocking. Even without that, CL30 remains ideal for productivity and gaming stability, offering better performance than a C40-36 kit while delivering a superior experience.

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Ikarus_ORG
Member
226
10-17-2023, 08:09 PM
#3
cl is primarily designed for IC binning rather than delivering significant performance gains. Its main role lies in optimizing for specific chips, with most efficiency improvements coming from tighter subsets that boards automatically apply. Recent updates suggest Hynix is advancing performance further, offering clear guidance for tuning. Based on available resources, 6000c30/32 timings appear unbinned, similar to OEM HMCG78AGBUI081N 5600C46 dies. 6000c28 seems suboptimal, while 6000c26 is suitable for advanced users aiming for higher clocks like 8000c28 exceeding 1.7V. Overall, noticeable performance differences are unlikely unless pushing extreme limits, making it more of an enthusiast project than a practical choice. The recommended path is to purchase the cheapest 6000c30/32 and apply BuildZoid timings, achieving around 90-95% of the desired results.
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Ikarus_ORG
10-17-2023, 08:09 PM #3

cl is primarily designed for IC binning rather than delivering significant performance gains. Its main role lies in optimizing for specific chips, with most efficiency improvements coming from tighter subsets that boards automatically apply. Recent updates suggest Hynix is advancing performance further, offering clear guidance for tuning. Based on available resources, 6000c30/32 timings appear unbinned, similar to OEM HMCG78AGBUI081N 5600C46 dies. 6000c28 seems suboptimal, while 6000c26 is suitable for advanced users aiming for higher clocks like 8000c28 exceeding 1.7V. Overall, noticeable performance differences are unlikely unless pushing extreme limits, making it more of an enthusiast project than a practical choice. The recommended path is to purchase the cheapest 6000c30/32 and apply BuildZoid timings, achieving around 90-95% of the desired results.

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Anselhero
Senior Member
582
10-19-2023, 02:39 AM
#4
The initial response latency must meet or fall below 10ns. I evaluated using CAS latency adjusted for speed, ensuring values at 6000MHz or lower.
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Anselhero
10-19-2023, 02:39 AM #4

The initial response latency must meet or fall below 10ns. I evaluated using CAS latency adjusted for speed, ensuring values at 6000MHz or lower.

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Juan2610
Posting Freak
875
11-01-2023, 07:32 AM
#5
i haven't really focused on performance tuning yet, since i've mostly worked with high-frequency stability and won't bother tightening components until i hit an imc wall. I'm still struggling with my quad stick DDR3 3300C13 on my out-of-commission Z97x SOIC and my RAM all acts poorly, so i can't loosen the cl as much as i can with the tightest one. Any data i have would be within a small margin of error, around 2-3cl differences. Even then, i know it's the memory chips that count, not the mostly unnecessary primaries—especially trcd, which is more important than the other cas latency. I still chase low CL values just for fun and to justify running high voltage, but if i were more practical, i wouldn't. CL latency is just hype; it only matters when you're benchmarking and barely improves things. Ask any other experienced maker—they'd agree, and the videos i linked are just that: memoc. The 7600C38 will naturally run slower by default, and even if it were 7600C28 (which is possible with those binned 6000C26 sticks, but still over 1.6v), it would still lag due to desync UCLK penalties. The main reason for high-frequency use is lower VSOS, since the SOIC draws a fair amount of power.
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Juan2610
11-01-2023, 07:32 AM #5

i haven't really focused on performance tuning yet, since i've mostly worked with high-frequency stability and won't bother tightening components until i hit an imc wall. I'm still struggling with my quad stick DDR3 3300C13 on my out-of-commission Z97x SOIC and my RAM all acts poorly, so i can't loosen the cl as much as i can with the tightest one. Any data i have would be within a small margin of error, around 2-3cl differences. Even then, i know it's the memory chips that count, not the mostly unnecessary primaries—especially trcd, which is more important than the other cas latency. I still chase low CL values just for fun and to justify running high voltage, but if i were more practical, i wouldn't. CL latency is just hype; it only matters when you're benchmarking and barely improves things. Ask any other experienced maker—they'd agree, and the videos i linked are just that: memoc. The 7600C38 will naturally run slower by default, and even if it were 7600C28 (which is possible with those binned 6000C26 sticks, but still over 1.6v), it would still lag due to desync UCLK penalties. The main reason for high-frequency use is lower VSOS, since the SOIC draws a fair amount of power.