10 vs 18 cores cpu heat?
10 vs 18 cores cpu heat?
In fact, this could become unclear because it relies on several details: the actual meaning of the temperature report (single value, per core, average?), which cores are engaged for the job. If the CPUs share the same die—such as having 10 cores with 8 fused together—or if they use separate dies, the situation changes. For instance, if the temperature reading reflects an average across active cores and the task targets distant cores, there’s a wider area to release heat. Assuming the die is larger on the 18-core version, more space exists for heat dissipation, which could keep the 18-core cooler even if it generates slightly more heat than the 10-core setup.
I just discovered the white sheets which might clarify some points: https://www.intel.com/content/dam/www/pu...-vol-1.pdf Page 35, Section 5.1. My take is that VCCIO/VCCSA stays connected to the IVR, appearing as voltage rails from the processor rather than board-supplied power. The VDIMM is still created by the board and doesn’t reach the FIVR according to this view. It notes one main rail (VCCIN) and a second for memory, mentioning VCCD (VDIMM). I might be misinterpreting this, so a fresh perspective would be helpful. Previously, I thought Skylake-X’s IVR worked the same as earlier models. If this isn’t accurate, I’ll need to revisit it.
It also indicates the same outcome, though X299 boards lacking KBL-X support (like Asrock X299-ITX) retain VCCSA VRM. If it isn't required for Skylake-X, then especially on such a compact board Asrock should redirect the VCCSA phase to VCCIN rather than VCCIN, assuming engineering samples accommodate KBL-X and possess a VCCIO rail, and reconfigure the ISL69138 controller to 7+0 mode instead of its current 6+1 setting. This adjustment would help lower heat output for this small device.