Why does lion cove exist?
Why does lion cove exist?
Lion Cove offers a strong performance profile. It excels in efficiency, holds the ST and IPC titles while delivering nearly double the power compared to Zen 5. Skymont, on the other hand, boasts about 1.02x the IPC of Raptor Cove and can achieve solid clock speeds. The space requirements are impressive—Skymont operates under less than 3mm², whereas Lion Cove is closer to double that size (around 5mm² for Zen 5). If Intel had not included Lion Cove, a 32-core Skymont CPU would have been the optimal choice for top-tier efficiency, lower manufacturing costs, and better power efficiency. This architecture could realistically reach around 13.6 million ST performance at clock speeds of 4.8–5 GHz, delivering gaming and ST scores comparable to Alder Lake+ while being more suitable for laptops with many cores and threads. The idea that Skymont struggles at higher clocks is debatable; comparisons like SD865 vs SD870 show tuning differences rather than fundamental flaws. This concept could significantly improve efficiency and performance in the market, especially for budget-conscious users seeking high efficiency.
It seems the issue stems from Intel P cores and E cores originating from separate technology paths. P cores were initially part of the Intel Core series, whereas E cores utilized components from the Atom line. Their architectures differ, causing compatibility challenges. For instance, in early 12th-gen models, P cores contained hidden Avx512 support while E cores lacked it entirely. Intel concealed this via microcode, and later removed all Avx512 instructions. You can activate them using modified BIOS on 12th-gen chips featuring a circular Intel logo. There may also be connections to shared L2 caches and decode-launch microarchitecture problems, though I don’t have concrete statistics on these matters.
Many good questions. I'll pick this bit for now because it is easier. Look at AMD C vs c cores for a close parallel to what you describe. The process of tuning smaller cores for efficiency prevents them from clocking up. To make them clock up, they get big again and lose efficiency. Make your choice which you optimise for. IPC is also a bit of an idealised measure. I think if you were to make a CPU from a lot of Skymont cores, as you load them up with consumer style workloads they'll fall off much faster from the ideal peak. The forest based CPUs target use cases not affected so much by that. Do you know of anyone doing perf vs power curves for them? Is your statement for a particular operating point? Edit: in general, where you made claims, please can you link to a reference demonstrating those claims so we at least are looking at the same info.
They're focusing on the highest ST performance and power usage under those conditions. It seems experts have verified this, especially with Intel's cluster setups. Even with small clusters of four cores, achieving 16 threads for gaming doesn't seem excessive. I was thinking about the SD865 vs SD870 line.
They utilize the same L2 cache, which is what contributes to their performance issues
For 12gen, P cores employs a 6-wide microarchitecture with six decoders, whereas E cores uses three decoders. This setup could negatively affect performance.