Talk about Arrow Lake here.
Talk about Arrow Lake here.
The design focuses on compatibility, allowing easy integration of new hardware. The goal seems to balance cost and flexibility rather than pushing performance limits. The modular approach supports upgrades without major redesigns. It’s not just about raw numbers but about maintaining efficiency and adaptability across different workloads. The shift in process nodes reflects a move away from Intel’s previous strategies, emphasizing efficiency over sheer speed. The transition between generations also highlights the industry’s evolving priorities.
Holly, it looks like AMD is broadcasting live right now. I'm not having dinner tonight.
I'm not part of the Intel team or leadership, but if I had to infer, the choice to use older components likely aimed to simplify manufacturing. The core motivation behind AMD's chiplets isn't solely about adding cutting-edge capabilities to a chip. It primarily offers greater adaptability overall. Both Zen 4 and Zen 5 share the same IO die, eliminating the need for a complete silicon redesign—this saves significant time. It also allows AMD to repurpose existing dies for different generations, streamlining production. This approach could potentially be reversed, but only if it aligned with financial goals. It seems cost-effective and practical, possibly reducing expenses by a few dollars per unit or even less. The main benefit might be accelerating time-to-market or ensuring a viable launch, rather than pure performance gains. Ultimately, Intel likely made the decision based on a comprehensive assessment of value and feasibility.
The lunar lake chip featured a more unified design, with the GPU and NPU integrated into the compute tile built on TSMC’s N3B. On Arrow Lake, the compute tile contained only CPU cores (on N3B), while graphics moved to a separate tile on TSMC N5P—possibly explaining its Xe architecture. The NPU was placed in the SoC tile on TSMC N6, matching the same node as Meteor Lake’s graphics tile. In essence, Lunar Lake included only the newest cores on a larger tile, while other parts relied on components from Meteor Lake. These alternative tiles tend to be more affordable and less critical for desktop builds. Originally planned for Intel 20A, this architecture shifted to an external node (TSMC) to focus on Intel’s 18A process, which is a strategic move. Integrated components are those built directly into the CPU, whereas discrete ones require external add-ons. Lion Cove stands out as a premium CPU with an 8-wide decoder on an x86 platform (Zen 5 uses fewer decoders). It delivers strong single-thread performance and is energy efficient at 15W, though it lags behind recent Zen and Apple chips. For more details on its features, check the links provided. The modular design of its CPU has introduced latency and bandwidth challenges, similar to memory issues seen in Intel’s recent designs. Their approach supports HT as a simple block and offers ample cores for SIMT tasks, making it suitable for high-performance workloads. A Lion Cove variant with SMT support is expected in future Xeon releases—ideal if gaming is your priority.
Older or smaller NPUs and iGPUs have been used because desktop CPUs usually include dedicated GPUs, offering much higher performance and efficiency. AMD followed a comparable strategy with their Zen 4 and Zen 5 chips, producing compact iGPUs. In laptops, upgrading to faster or newer iGPUs makes more sense since they often serve as the sole graphics component.
I haven't located clear die shot comparisons that fully capture this, but from what I recall, MTL featured P cores and E cores spread across separate chiplets, whereas ARL had everything on a single chiplet. That aligns with Lunar Lake improvements. I've also heard that latency on LNL is significantly lower than in MTL setups. It seems there might have been adjustments to the Foverous interconnect, but ARL currently appears to rely on a more unified design. My assumption was that Intel was fine-tuning LNL for optimal efficiency, leading to a distinct architecture compared to ARL. However, I wasn't sure about the exact timeline for AMD's transition—was it a deliberate shift to N3P, or just a timing adjustment? It seems AMD has been developing ARL for some time, even if the process node changed. Intel is now using TSMC's 3 nm technology, which could offer better efficiency than AMD's previous nodes. The power efficiency gap might stem from architectural differences rather than just manufacturing advances.
The decision on the node for Zen 5 probably represented a middle ground. The N4 option was more affordable compared to N3B, and AMD seemed confident they could meet their objectives without a complete node reduction. For Intel, there were numerous challenges ahead to keep up with AMD across all fronts—completing such a shift in just one generation would have been extraordinary. Looking at their first modular design, the lack of significant performance drops is noteworthy. Zen delivered much lower speeds than Bulldozer. The FX 9590 ran at 5GHz, while the R7 1800X barely surpassed 4GHz. It wasn’t until Zen 3 introduced the 5950X that a consumer CPU could reliably hit 5GHz. The 285K managed to reach 5.7GHz with only a 5% drop from the 6GHz of the 14900K, and it achieved this efficiently. Intel’s major architectural changes while preserving those speeds are clearly a significant accomplishment.
The meteor lake compute tile on Intel 4 included both P and E cores. The SoC tile on TSMC N6 also featured additional E cores, enabling the entire tile to be downsized. This results in three CPU levels. Lunar lake and Arrow Lake only contain CPUs within the compute tile, not on the SoC tile. Performance gains came from extra cache layers and a different core layout—E cores no longer share the ringbus or cache with P cores. It's worth noting that LNL lags behind ARL mainly because of LPDDR5 memory versus standard desktop DDR5. I doubt Foveros is responsible for the latency differences or product variations, though I'm unsure about that. All components remain identical in Lion Cove and Skymont on the same manufacturing process. Core configurations differ inside the tiles, and Arrow Lake uses more cache, which increases power use and die size. Zen 5 offers a broad range of options: desktop (9000 series) and Epyc N4 (possibly N4P or N4X), while Zen 5+5c mobile is N4 (possibly N4X). Zen 5c on Epyc Turin is N3. Arrow Lake was originally intended for Intel 20A, but that option was removed, forcing a switch to TSMC. AMD planned Zen 5 to support both nodes for better cost efficiency across segments. This also reflects changes in how the chip is physically assembled. Lunar lake remains efficient, though it underperforms compared to Zen 4/5 mobile and Apple’s monolithic designs. Intel opted for a tiled architecture, which has its own drawbacks.
Intel seems to be facing some challenges lately. It appears they're putting in effort, but not necessarily excelling in their current area. Their performance hasn't kept pace with competitors who have adapted quickly over the past decades. There might be underlying factors affecting their progress, such as the specific challenges with Arrow Lake or perhaps compatibility issues with TSMC's latest processes. While AMD, Apple, Qualcomm, and Nvidia have all leveraged TSMC's capabilities effectively, Intel has struggled to match their agility. The company's market valuation doesn't seem sufficient to justify maintaining its own fabrication operations. Switching to TSMC might be a strategic move, but Intel's current scale and resources are hard to match. The recent Qualcomm partnership seems more logical, yet Intel's historical approach to foundry management has clearly fallen short. It's worth noting that AMD has made significant strides with chiplet designs and unified core architectures, offering efficiency benefits that Intel hasn't fully capitalized on. The company's recent development timeline also raises questions about their ability to deliver strong results, especially given past delays with the 14th-gen chip. While AMD's innovations are impressive, Intel still holds a competitive edge in certain areas, particularly with their silicon interposers and overall integration strategy.
Company went too much into "give investors money asap" mode instead of focusing on engineering for way too long (just see how long they were stagnated), now they're playing catch up. They're improving with every generation, but not enough to be 100% competitive. Could be, we can't say with 100% certainty tho. Intel's idea of the IDF is great, and fabbing for other companies, specially in the US, is a great thing that will be really profitable in the future. You don't have many leading semiconductor companies, TSMC has the monopoly of the current most advanced node, with Samsung and some couple others lagging a bit behind. Intel's foundries as a company focused solely on competing with TSMC is a great idea. Intel making use of said foundry or not is a totally different topic. They already moved partially to TSMC, cheaper parts being on cheaper nodes from them makes the TCO even lower. You really should try to not drink the media kool-aid all the time. Intel is not in a great time, but it's not burdened at all, don't buy into the drama. It is good, just not as good as the competition, and also a CPU is not only the actual core design, there are many parts around it that dictate if a product is good or not. But investors would. They don't care about you, they care about making shareholders happy, and those require new products every year or so. Intel only has two µarches currently, one for their E-cores and another one for their P-cores. Both are used in the consumer space and xeons. A bit off-topic but not much: I'm not sure if it's just an impression, but it feels like you're really emotionally involved with all things Intel. If so, why? It's just a company that's going through a bad phase now, they'll eventually recover and become a shitty greedy company, until someone surpasses then again, and so on and so on. There's no reason to try to dig that deep into such things lol