Refining the infinite weave
Refining the infinite weave
Check your board specs and review the SOC/VDDG documentation. Consider adjusting both stability parameters or just one at a time. Safe voltage ranges depend on your design; consult datasheets. Look into tweaking other settings like current limits or thermal management. For stress testing, run Prime95 as a baseline and then apply incremental loads to identify failure points.
There aren't significant voltage adjustments that improve FCLK stability for regular use. The 1.8V rail offers some benefit but isn't sufficient for higher stability. SOC voltage mainly supports the memory controller at faster speeds, while VDDG isn't a major concern. If stability problems stem from FCLK, try running Y cruncher 1B at 1900 and 1866 FCLK to see if performance improves. If the score jumps noticeably, it suggests the clock speed is too high and nothing further can be done.
VDDG IOD and VSOC adjustments suggested. Try 1.15v SOC with 1.065v VDDG IOD. Consider switching SOC to levels 3 or 4.