F5F Stay Refreshed Hardware Desktop RAM OC Issue MSI + Ryzen + Corsair

RAM OC Issue MSI + Ryzen + Corsair

RAM OC Issue MSI + Ryzen + Corsair

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ColeCreeper99
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42
05-29-2019, 10:40 PM
#11
When all options failed and the output stayed under 3000, it was likely due to clock speed limits.
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ColeCreeper99
05-29-2019, 10:40 PM #11

When all options failed and the output stayed under 3000, it was likely due to clock speed limits.

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M
megsterz
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208
06-02-2019, 10:58 AM
#12
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megsterz
06-02-2019, 10:58 AM #12

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JonoGaimz
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63
06-03-2019, 06:22 PM
#13
The FCLK represents the maximum speed at which data can travel between components. If an interconnect has a certain FCLK, it won't handle very high speeds efficiently, particularly when multiple devices are involved. Apologies for the unclear explanation—I'm a bit delayed and need to rest now.
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J
JonoGaimz
06-03-2019, 06:22 PM #13

The FCLK represents the maximum speed at which data can travel between components. If an interconnect has a certain FCLK, it won't handle very high speeds efficiently, particularly when multiple devices are involved. Apologies for the unclear explanation—I'm a bit delayed and need to rest now.

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Columbia0405
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34
06-03-2019, 06:58 PM
#14
The issue isn't related to FCLK limits at 1533. I haven't encountered anyone facing FCLK restrictions below 1733.
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Columbia0405
06-03-2019, 06:58 PM #14

The issue isn't related to FCLK limits at 1533. I haven't encountered anyone facing FCLK restrictions below 1733.

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S
smag30
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140
06-03-2019, 07:50 PM
#15
I attempted 16-16-16-38-58 (1T). Do you notice any pattern among these numbers? Additional note: I didn’t recognize this sequence. If it aids clarity, please consider leaving it as 2T for stability. Edited June 8, 2020 by ShrimpBrime
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smag30
06-03-2019, 07:50 PM #15

I attempted 16-16-16-38-58 (1T). Do you notice any pattern among these numbers? Additional note: I didn’t recognize this sequence. If it aids clarity, please consider leaving it as 2T for stability. Edited June 8, 2020 by ShrimpBrime

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TiTansio11
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189
06-04-2019, 11:04 AM
#16
yeah, I read about it, tRAS should be CL+20 minimum and tRC = tRAS+20 minimum
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TiTansio11
06-04-2019, 11:04 AM #16

yeah, I read about it, tRAS should be CL+20 minimum and tRC = tRAS+20 minimum

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spidersaur187
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201
06-05-2019, 02:59 AM
#17
Really, even with 2T the device doesn't transmit when the frequency exceeds 3000MHz, regardless of timing or voltage. It seems like a small success in silicon luck. At least I managed stability at 3000MHz CL15 Smile. Unless you have additional advice.
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spidersaur187
06-05-2019, 02:59 AM #17

Really, even with 2T the device doesn't transmit when the frequency exceeds 3000MHz, regardless of timing or voltage. It seems like a small success in silicon luck. At least I managed stability at 3000MHz CL15 Smile. Unless you have additional advice.

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LazzaOner
Junior Member
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3
06-05-2019, 03:30 PM
#18
This memory kit isn't designed to handle higher voltages; increasing the voltage won't improve performance since it will simply draw more current.
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LazzaOner
06-05-2019, 03:30 PM #18

This memory kit isn't designed to handle higher voltages; increasing the voltage won't improve performance since it will simply draw more current.

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M
moonhoax
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148
06-12-2019, 09:08 AM
#19
It's a shame, but do you think it's worth adjusting the timing? For now, I was able to achieve something stable like this.
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moonhoax
06-12-2019, 09:08 AM #19

It's a shame, but do you think it's worth adjusting the timing? For now, I was able to achieve something stable like this.

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AdamPlayzxXMc
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52
06-21-2019, 03:58 AM
#20
Definitely adjust them if feasible. Cl12 could be a bit loose.
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AdamPlayzxXMc
06-21-2019, 03:58 AM #20

Definitely adjust them if feasible. Cl12 could be a bit loose.

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