Major issues with Ballistix OC troubleshooting
Major issues with Ballistix OC troubleshooting
Hello! I've been working on extracting 4000 MHz from the Crucial Ballistix BL8G32C16U4B.M8FE1 trims for the second day. I've already tested 27 different settings, and this includes the times I recorded right after taking notes—I’ve actually tried over 40. It seems challenging to get stable results without errors in the memtest. Anyone have a clue about what might be going wrong? I've attached a table with the tested timings.
From Buildzoid videos, it seems only a few reached 5000MHz across the Ballistix series beginning at 3000MHz. It looks like a 4000MHz might be achievable, but I suspect my BIOS configuration is off.
Many of these connectors support up to 5000MHz, though stability varies. 4000MHz is likely reachable for regular use on most models, especially with Ryzen. I purchased 64GB that handle 3800CL14 at an XMP setting of 3200CL16.
These are my configuration details, taken from an ASUS motherboard. The settings appear to be displayed in the location where they were found. This board supports Ryzen processors... perhaps adjust it further as well. Advanced/AMD CBS/CPU Common Options -> ECC Disabled MemAddrCmdSetup = 0 MemCsOdtSetup = 0 MemCkeSetup = 0 Extreme Tweaker's Paradise ___________________________________ VTTDDR Voltage = 1/2 DRAM Voltage VPP_MEM Voltage = consistently 2.5V or 2.52V because of V droop DRAM CTRL REF Voltage on CHA/CHB = Vref (CHA/CHB) in DRAM Calc DRAM R1/R2/R3/R4 Tune = 0 Sense MI Skew = Disabled (Super I/O Clock Skew in DRAM Calc) Advanced ... AMD CBS/CPU Common Options/Prefetcher Settings -> L1/L2 Stream HW Prefetcher = Enabled AMD CBS/DF Common Options - Memory Clear = Disabled AMD CBS/DF Common Options/Memory Addressing -> Memory Interleaving Size = 512 Bytes AMD CBS/UMC Common Options/DDR4 Common Options/Phy Configuration/PMU Training -> PMU Pattern Bits = A -> PMU Pattern Bits Control = Manual -> FFE Write Training = Enabled -> DFE Read Training = Enabled AMD CBS/UMC Common Options/DRAM Memory Mapping -> BankGroupSwap (BGS) = Disabled -> BankGroupSwapAlt (BGS alt) = Enabled -> Adress Hash CS = Enabled (Memory interleaving = Channel) I currently run 3666MHzCL16 just because 3733MHzCL14 or 3800MHzCL14 needs 1.5V. That should be sufficient for everyday use but I haven’t really needed to push it higher. Make sure ECC is turned off. Even without ECC support, this will aid initialization during setup. Try experimenting with protODT as it significantly impacts stability, though it doesn’t affect speed. Various settings might improve reliability without compromising performance.
3200MHz CL16 combines parts from top "C9" dies like C9BJZ and lower-quality "D9" options such as D9VPP. Many people overestimate its performance. While it's more likely to yield better results than CJR, still significant issues remain. By the way, Rev.E struggles with tight tRP and tRCD—consider trying 20-23-23-46.