Dram voltage, VCCIO and SA in timing optimization. (B Die)
Dram voltage, VCCIO and SA in timing optimization. (B Die)
I'm checking the timing options for your Trident Z at 4000Mhz. The current settings are 16-16-16-36 with 1.44dram and 1.262VCCIO. You're considering lowering the timing to 15-16-16-35, similar to Gskill's 4000 CL15 kit. Decide where to begin—boost both the voltage and SA, or just increase the SA increment?
9700K illumination at 5.0Ghz, featuring a 1.0 AVX offset (1.32V), delivering stable performance capable of clearing prime 95 small FTTs with max 3200 CL14 EVGA 2080 TI at 4x8Gb.
Are you aiming for 4000MHz while using 3200MHz memory? That will require higher voltage to reach it.