F5F Stay Refreshed Hardware Desktop Does high CAS latency occur when using slow DDR?

Does high CAS latency occur when using slow DDR?

Does high CAS latency occur when using slow DDR?

B
BlackVeilEwan
Member
138
10-27-2022, 01:54 AM
#1
I'm assembling an arrow lake rig on a Z890 Asrock motherboard (Pro RS). The QVL memory list indicates G.Skill 8400 CAS 40 2x24GB sticks are compatible. If I switch to DDR 5600 for stability, would the CAS speed drop into lockstop or remain at the slower 40 with high latency? On DDR 5600 sticks, CAS can typically be reduced to 30-32.
B
BlackVeilEwan
10-27-2022, 01:54 AM #1

I'm assembling an arrow lake rig on a Z890 Asrock motherboard (Pro RS). The QVL memory list indicates G.Skill 8400 CAS 40 2x24GB sticks are compatible. If I switch to DDR 5600 for stability, would the CAS speed drop into lockstop or remain at the slower 40 with high latency? On DDR 5600 sticks, CAS can typically be reduced to 30-32.

S
SayNoToNWO
Posting Freak
879
11-02-2022, 08:12 PM
#2
What makes DDR5-8400MHz RAM worth considering? You can easily find DDR5-6000MHz options that are widely recognized as ideal for most DDR5 systems (both Intel and AMD). In fact, you can also choose any DDR5-6000MHz or slightly faster memory with low latency—provided it includes Intel's X.M.P branding—to ensure compatibility with your setup.
S
SayNoToNWO
11-02-2022, 08:12 PM #2

What makes DDR5-8400MHz RAM worth considering? You can easily find DDR5-6000MHz options that are widely recognized as ideal for most DDR5 systems (both Intel and AMD). In fact, you can also choose any DDR5-6000MHz or slightly faster memory with low latency—provided it includes Intel's X.M.P branding—to ensure compatibility with your setup.

A
Axduda
Junior Member
15
11-02-2022, 10:06 PM
#3
Yes, I can try. However, I would appreciate receiving a specific response to the issue presented.
A
Axduda
11-02-2022, 10:06 PM #3

Yes, I can try. However, I would appreciate receiving a specific response to the issue presented.

G
gemoore
Junior Member
46
11-04-2022, 12:07 PM
#4
Cas and other delays increase with faster RAM, allowing modules to stay properly synchronized. Lowering frequency also reduces latency, meaning you can adjust Cas and related settings correctly. Since high-speed RAM likely doesn’t support XMP at 5600MHz, manual adjustments per JEDEC standards are recommended.

PS. Cas latency isn’t the only factor—it’s just one part of overall performance. Changing just Cas won’t significantly improve RAM speed or system efficiency; other timings and settings need modification too.
View: https://www.youtube.com/watch?v=H-Ofj5nIYfY
G
gemoore
11-04-2022, 12:07 PM #4

Cas and other delays increase with faster RAM, allowing modules to stay properly synchronized. Lowering frequency also reduces latency, meaning you can adjust Cas and related settings correctly. Since high-speed RAM likely doesn’t support XMP at 5600MHz, manual adjustments per JEDEC standards are recommended.

PS. Cas latency isn’t the only factor—it’s just one part of overall performance. Changing just Cas won’t significantly improve RAM speed or system efficiency; other timings and settings need modification too.
View: https://www.youtube.com/watch?v=H-Ofj5nIYfY

C
COLIN20052012
Posting Freak
857
11-04-2022, 04:56 PM
#5
When addressing the query, it's important to note that G. Skill 48GB DDR5 8400 CL40 1.4 volt kits feature a True Latency of 9.524 nS. The relationship between Time, Single Data Rate (SDR) Frequency in GHz, and Column Latency is defined as TL equals Time divided by SDR Frequency multiplied by CL. Alternatively, the calculation can be expressed as: 1 second divided by 4.2GHz (Single Data Rate) times 40 (Column Latency) equals 9.524 nanoseconds (True Latency). In the broader context of DDR5 memory, although improvements in bandwidth have been made, a True Latency of 8 nS remains a significant challenge for SDR, DDR, DDR2, DDR3, DDR4, and especially DDR5. Typical benchmarks are as follows:

- DDR 400 @ CL2 = 10 nS
- DDR2 800 @ CL4 = 10 nS
- DDR3 1600 @ CL8 = 10 nS
- DDR4 3200 @ CL16 = 10 nS
- DDR5 6400 @ CL32 = 10 nS

Beyond performance metrics, for quick comparisons, a latency between 7.5 to 8 nS is considered excellent, while 8 to 8.5 nS offers solid speed, 8.5 to 9 nS is acceptable, 9 to 10 nS is average, and 11 to 12 nS indicates subpar performance. Prices exceeding 12 nS are generally not recommended unless budget constraints allow.

As highlighted by AsCountMike, larger DDR5 kits tend to have more relaxed timing parameters. For instance, the 48GB DDR5 8400 kit mentioned shows a range of 40-52-52-134, indicating that DDR5 technology is still evolving toward full maturity.

Despite this, using a Z890 motherboard, it's possible to manually downclock the memory to 6000 MHz, as suggested by Lutfij, and then fine-tune the Primary Timing to 28-40-40-122, achieving a True Latency of 9.333 nS. This is marginally quicker than the standard setting of 9.524 nS. At this lower frequency, you might also reduce the DRAM voltage from 1.4V down to approximately 1.38V or even lower to 1.36-1.35V.

Alternatively, trying a configuration at 6000 MHz with settings 27-39-39-121 could yield a True Latency of 9.0 nS (about 5.82% faster than the standard), though it may require maintaining the voltage at 1.4V. Running multiple memory tests is essential to confirm stability under these optimized parameters.

As long as the solution remains cost-effective, this method has been used to install memory that outperforms the CPU's IMC capabilities, allowing for downclocking to ensure compatibility and stability while lowering the operating voltage, all while keeping temperatures lower. This strategy also supports future CPU upgrades with faster IMCs.
C
COLIN20052012
11-04-2022, 04:56 PM #5

When addressing the query, it's important to note that G. Skill 48GB DDR5 8400 CL40 1.4 volt kits feature a True Latency of 9.524 nS. The relationship between Time, Single Data Rate (SDR) Frequency in GHz, and Column Latency is defined as TL equals Time divided by SDR Frequency multiplied by CL. Alternatively, the calculation can be expressed as: 1 second divided by 4.2GHz (Single Data Rate) times 40 (Column Latency) equals 9.524 nanoseconds (True Latency). In the broader context of DDR5 memory, although improvements in bandwidth have been made, a True Latency of 8 nS remains a significant challenge for SDR, DDR, DDR2, DDR3, DDR4, and especially DDR5. Typical benchmarks are as follows:

- DDR 400 @ CL2 = 10 nS
- DDR2 800 @ CL4 = 10 nS
- DDR3 1600 @ CL8 = 10 nS
- DDR4 3200 @ CL16 = 10 nS
- DDR5 6400 @ CL32 = 10 nS

Beyond performance metrics, for quick comparisons, a latency between 7.5 to 8 nS is considered excellent, while 8 to 8.5 nS offers solid speed, 8.5 to 9 nS is acceptable, 9 to 10 nS is average, and 11 to 12 nS indicates subpar performance. Prices exceeding 12 nS are generally not recommended unless budget constraints allow.

As highlighted by AsCountMike, larger DDR5 kits tend to have more relaxed timing parameters. For instance, the 48GB DDR5 8400 kit mentioned shows a range of 40-52-52-134, indicating that DDR5 technology is still evolving toward full maturity.

Despite this, using a Z890 motherboard, it's possible to manually downclock the memory to 6000 MHz, as suggested by Lutfij, and then fine-tune the Primary Timing to 28-40-40-122, achieving a True Latency of 9.333 nS. This is marginally quicker than the standard setting of 9.524 nS. At this lower frequency, you might also reduce the DRAM voltage from 1.4V down to approximately 1.38V or even lower to 1.36-1.35V.

Alternatively, trying a configuration at 6000 MHz with settings 27-39-39-121 could yield a True Latency of 9.0 nS (about 5.82% faster than the standard), though it may require maintaining the voltage at 1.4V. Running multiple memory tests is essential to confirm stability under these optimized parameters.

As long as the solution remains cost-effective, this method has been used to install memory that outperforms the CPU's IMC capabilities, allowing for downclocking to ensure compatibility and stability while lowering the operating voltage, all while keeping temperatures lower. This strategy also supports future CPU upgrades with faster IMCs.