Discussion about PCIE lane splitting
Discussion about PCIE lane splitting
Details about the Asus B85M-Gamer motherboard are limited online. The manual offers minimal guidance on PCIe connections. What I discovered is that the only active slot is the 16x PCIe 3.0 lane configuration. My friend plans to install a single PCIe 2.0 1x Wi-Fi card, expecting it to use just 8 lanes. While I don’t expect major performance drops from that change, I’m concerned about potential protocol downgrades—specifically whether the system will switch from PCIe 3.0 to 2.0, possibly affecting the GPU. My main questions are: How are the lanes allocated and switched? Should I be concerned if the host controller reduces the speed to 2.0? If I connect a 2.0 device in another slot, will the GPU continue operating at PCIe 3.0? I’d appreciate any reference to datasheets or manuals that explain onboard switchers and lane usage. Anyone know where Asus might provide this information?
Intel maintains detailed records on PCIe lanes. Relevant resources include: Core i7 4790K page at Ark, and the B85 chipset documentation. For contemporary systems, PCIe x16 slots typically originate from the CPU, while x1 slots usually come from the chipset. For confirmation about your motherboard configuration, refer to the official manual—it will specify which slots belong to which component.
Hi @Chiyawa, I already had the solution, but appreciate you getting back to me. Thanks for the help—I figured it out once I shared the post. The motherboard manual doesn’t provide much detail, but I ended up on the specific page you mentioned and discovered the datasheet for the B85. That’s where I learned about the chipset PCIE lanes.