DDR4 3600/4000MHz memory setup
DDR4 3600/4000MHz memory setup
One after the other, it seems likely to be stable, but testing will be necessary to confirm. Of course, I can elaborate later, though here’s a brief summary of the timing details: tRRD and tRRD_L manage how rapidly consecutive read commands are sent—ideally 4 each, though tRRD_L should generally be bigger, especially for Hynix chips where the standard tRRD is around 6. tFAW defines the duration for four tRRD commands; set it to 16 without issue. tRFC and tREFI control memory refresh timing and intervals. Aim for minimal tRFC and maximal tREFi. With cooling, tREFi can reach 65535, while tRFC may be limited to 50k or 30k based on temperature. tCKE is typically set to 4, though it has little impact. tCWL represents CAS latency for writes; match it to tCL for full stability, otherwise you might see performance drops of a few ticks. tRDRD_sg and tRDRD_dg specify back-to-back read durations—keep tRDRD_dg at 4, tRDRD_sg higher (around 7 or 8). tRDWR_sg and tRDWR_dg define intervals between reads and writes; usually 12 each. tWRWR_sg and tWRWR_dg indicate back-to-back write times—keep tWRWR_dg at 4, tWRWR_sg higher (7-8). tWRRD_sg and tWRRD_dg reflect write-to-read gaps, which depend on the chip; I can’t advise much beyond that. All secondary timings ending in sd or dd are irrelevant here—ignore them or set to 1. tRDPRE is Read to Pre-Charge, it minimally affects performance but may need setting if stability is critical. tWRPRE denotes Write to Pre-Charge, or the recovery time; adjust based on chip characteristics and timing values.
Mate you are amazing thank you so much I’ve being reading a watching video about timing and it’s was like a different language you just made it simple for me to understand thank you ok I will we do some testing and get back to you then we can play with some timings