Adjust your DDR5 settings for Hynix A-Die.
Adjust your DDR5 settings for Hynix A-Die.
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- There are a few points I’d like to highlight upfront. The die shows a lot of inconsistency in the subtimings, so you can’t just copy and paste my settings. You’ll need to adjust them manually to get the best results. While I can share some general advice, you’ll have to run your own tests and fine-tune everything.
- Usually I stick with 123456, but there’s little gain in pushing performance further. Going higher can cause unexpected problems down the line. If it’s already set, I’d probably leave it at 100000—it’s not worth the trouble for much better speed.
- Regarding timing: good chips should handle 400 and 300 for tRFC2 and tRFCpb respectively, with 444 and 333 being more dependable.
- The tRRD settings differ widely between models. Top-tier chips usually aim for 4-7 on s and l, while lower-end ones often settle around 8-9. These are especially tricky to nail.
- WTR timing isn’t accurate and is managed by the tRTP in BIOS (should be set to tRDPRE). It tends to change with frequency.
- The really strong chips at 7200 should target 8, whereas weaker ones might cap around 16.
- For tCWL, there’s a lot of variation—if you’re lucky it can cut CAS latency in half; otherwise, set it lower.
- tCKE usually needs 16 to be stable, and it only fails at TM5 1usmus_v3 if tCKE is too low. It has minimal impact on speed but it’s worth tweaking.
- tRDRD at 7200 can stabilize around 14-7 for sg-dg; otherwise it might be 16-8, rarely working.
- The dr-dd settings don’t apply here either—leave them auto or set to 1, which affects all the tRTs.
- tRDWR can sometimes hit 19-19 for sg-dg, but often it’s 20, and if you’re unlucky it might not work at all.
- tWRRD actually controls the tWTR settings, though these are very sensitive. Some chips run 60-44 for sg-dg, while others (like mine) struggle with 70-50.
- Adjusting your primary timings will influence these values.
- tWRWR is responsible for setting tWTR, but there’s a huge range—some chips do 60-44, others (including mine) can only get 70-50.
- tWRPRE—the timing that defines tWR—is heavily influenced by CAS latency. It’s usually fine at 50, but may drop to around 44 or struggle to go lower.
- These settings all differ a lot, so results will vary.
That's correct, the primaries don't significantly boost performance on their own. Some timing changes are influenced by them. Tcwl also consumes a lot of power when you crank it up, but whether it outperforms Cl or matches its impact depends on the specifics.
Intel’s primary timings play a big role in shaping the minimums of tertiary settings. Sometimes I adjust CAS latency with a perfectly tuned setup, but it stops training because the subtimings become too erratic. A bit less per clock, yet you can still get solid results with a strong system, so the overall impact stays similar. Regarding the "gobbling volts" approach, I favor setting the maximum voltage first and then reducing timings, which makes a difference less critical. Not quite. tWR is similar to tWRRD—it’s a calculated timing based on tCL, tWRPRE, and tWRPDEN. tWRPDEN influences write delay during power-down, but it usually doesn’t change performance much. On the other hand, tWRPRE does affect performance. To ensure the ASRock Timing Configurator reads correctly, match tWRPDEN with tWRPRE; otherwise, tweaking just one is fine.
Looking for the top app to check memory stability? Try tools like MemTest86 or Realm Memory Test—they’re widely regarded as reliable options.
I used a mix of 2 to 3 stress tests. My choice is Y Cruncher VST—it’s tough on the memory controller and tied to the highest achievable frequency. I also tried TestMem5 at 1usmus. I ran them for one and two hours, but getting three different opinions from different people helps clarify things.
Enhancing cache performance is a solid approach. It slightly reduces memory latency and boosts overall system speed. The drawback lies in the 13th generation chips, which only reached around 4.8 and 4.9GHz before instability at higher voltages, compared to the standard 4.5GHz. Achieving stability demands a significant core voltage, meaning undervolting might actually reduce the needed cache voltage rather than increase it. For successful cache overclocking, you must also boost the entire CPU's voltage, not just lower it.